[U-Boot] [PATCH 1/5] vybrid: add vybrid CPU support

Liu Hui-R64343 r64343 at freescale.com
Mon Apr 15 05:24:53 CEST 2013


>-----Original Message-----
>From: Wang Huan-B18965
>Sent: Friday, April 12, 2013 2:54 PM
>To: u-boot at lists.denx.de
>Cc: sbabic at denx.de; Liu Hui-R64343; Estevam Fabio-R49496; TsiChung Liew;
>Jin Zhengxiong-R64188
>Subject: [PATCH 1/5] vybrid: add vybrid CPU support
>
>The Vybrid devices are a family of Freescale's latest Dual Single
>Core offering with ARM Cortex A5 and CM4 based processors for
>Advanced Connected Radio, Entry Infotainment, and Cluster as well
>as high end industrial and general purpose applications.
>
>This patch adds vybrid CPU support.
>
>Signed-off-by: TsiChung Liew <tsicliew at gmail.com>
>Signed-off-by: Jason Jin <Jason.jin at freescale.com>
>Signed-off-by: Alison Wang <b18965 at freescale.com>
>---
> Makefile                                         |   8 +
> arch/arm/cpu/armv7/vybrid-common/Makefile        |  46 ++
> arch/arm/cpu/armv7/vybrid-common/cpu.c           | 127 ++++
> arch/arm/cpu/armv7/vybrid-common/speed.c         |  37 ++
> arch/arm/cpu/armv7/vybrid-common/timer.c         | 140 +++++
> arch/arm/cpu/armv7/vybrid/Makefile               |  45 ++
> arch/arm/cpu/armv7/vybrid/asm-offsets.c          |  70 +++
> arch/arm/cpu/armv7/vybrid/clock.c                | 278 +++++++++
> arch/arm/cpu/armv7/vybrid/iomux.c                |  42 ++
> arch/arm/cpu/armv7/vybrid/lowlevel_init.S        | 128 ++++
> arch/arm/cpu/armv7/vybrid/soc.c                  |  42 ++
> arch/arm/include/asm/arch-vybrid/clock.h         |  41 ++
> arch/arm/include/asm/arch-vybrid/iomux.h         | 323 ++++++++++
> arch/arm/include/asm/arch-vybrid/serial-vybrid.h | 213 +++++++
> arch/arm/include/asm/arch-vybrid/sys_proto.h     |  30 +
> arch/arm/include/asm/arch-vybrid/timer.h         | 405 +++++++++++++
> arch/arm/include/asm/arch-vybrid/vybrid-pins.h   |  88 +++
> arch/arm/include/asm/arch-vybrid/vybrid-regs.h   | 735
>+++++++++++++++++++++++
> arch/arm/include/asm/global_data.h               |   3 +
> arch/arm/include/asm/mach-types.h                |  56 ++
> 20 files changed, 2857 insertions(+)
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/Makefile
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/cpu.c
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/speed.c
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/timer.c
> create mode 100644 arch/arm/cpu/armv7/vybrid/Makefile
> create mode 100644 arch/arm/cpu/armv7/vybrid/asm-offsets.c
> create mode 100644 arch/arm/cpu/armv7/vybrid/clock.c
> create mode 100644 arch/arm/cpu/armv7/vybrid/iomux.c
> create mode 100644 arch/arm/cpu/armv7/vybrid/lowlevel_init.S
> create mode 100644 arch/arm/cpu/armv7/vybrid/soc.c
> create mode 100644 arch/arm/include/asm/arch-vybrid/clock.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/iomux.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/serial-vybrid.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/sys_proto.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/timer.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-pins.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-regs.h
>
>diff --git a/Makefile b/Makefile
>index 12763ce..8a86951 100644
>--- a/Makefile
>+++ b/Makefile
>@@ -334,6 +334,9 @@ LIBS-y += test/libtest.o
> ifneq
>($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
> LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
> endif
>+ifeq ($(SOC),vybrid)
>+LIBS-y += $(CPUDIR)/vybrid-common/libvybrid-common.o
>+endif
>
> ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
> LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
>@@ -467,6 +470,10 @@ $(obj)u-boot.img:	$(obj)u-boot.bin
> $(obj)u-boot.imx: $(obj)u-boot.bin depend
> 		$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-
>boot.imx
>
>+$(obj)u-boot.vybrid: $(obj)u-boot.bin
>+		$(obj)tools/mkimage -n $(CONFIG_VYBRID_CONFIG) -T imximage \
>+		-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
>+
> $(obj)u-boot.kwb:       $(obj)u-boot.bin
> 		$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage
>\
> 		-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $<
>$@
>@@ -855,6 +862,7 @@ clobber:	tidy
> 	@rm -f $(obj)u-boot.kwb
> 	@rm -f $(obj)u-boot.pbl
> 	@rm -f $(obj)u-boot.imx
>+	@rm -f $(obj)u-boot.vybrid
> 	@rm -f $(obj)u-boot.ubl
> 	@rm -f $(obj)u-boot.ais
> 	@rm -f $(obj)u-boot.dtb
>diff --git a/arch/arm/cpu/armv7/vybrid-common/Makefile
>b/arch/arm/cpu/armv7/vybrid-common/Makefile
>new file mode 100644
>index 0000000..bee8850
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid-common/Makefile
>@@ -0,0 +1,46 @@
>+#
>+# Copyright 2012-2013 Freescale Semiconductor, Inc.
>+#
>+# See file CREDITS for list of people who contributed to this
>+# project.
>+#
>+# This program is free software; you can redistribute it and/or
>+# modify it under the terms of the GNU General Public License as
>+# published by the Free Software Foundation; either version 2 of
>+# the License, or (at your option) any later version.
>+#
>+# This program is distributed in the hope that it will be useful,
>+# but WITHOUT ANY WARRANTY; without even the implied warranty of
>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+# GNU General Public License for more details.
>+#
>+# You should have received a copy of the GNU General Public License
>+# along with this program; if not, write to the Free Software
>+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+# MA 02111-1307 USA
>+#
>+
>+include $(TOPDIR)/config.mk
>+
>+LIB     = $(obj)libvybrid-common.o
>+
>+COBJS	:= timer.o
>+COBJS	+= cpu.o
>+COBJS	+= speed.o
>+
>+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
>+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
>+
>+all:	$(obj).depend $(LIB)
>+
>+$(LIB):	$(OBJS)
>+	$(call cmd_link_o_target, $(OBJS))
>+
>+#######################################################################
>##
>+
>+# defines $(obj).depend target
>+include $(SRCTREE)/rules.mk
>+
>+sinclude $(obj).depend
>+
>+#######################################################################
>##
>diff --git a/arch/arm/cpu/armv7/vybrid-common/cpu.c
>b/arch/arm/cpu/armv7/vybrid-common/cpu.c
>new file mode 100644
>index 0000000..f99083e
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid-common/cpu.c
>@@ -0,0 +1,127 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <common.h>
>+#include <netdev.h>
>+#include <asm/errno.h>
>+#include <asm/io.h>
>+#include <asm/arch/vybrid-regs.h>
>+#include <asm/arch/clock.h>
>+#include <asm/arch/sys_proto.h>
>+
>+#ifdef CONFIG_FSL_ESDHC
>+#include <fsl_esdhc.h>
>+#endif
>+
>+static char *get_reset_cause(void)
>+{
>+	char *resetcause[32] = {"POR",
>+				"Cortex A5 WDOG Timer Reset",
>+				0,
>+				"CA5 WDOG reset",
>+				"CM4 WDOG reset",
>+				"JTAG HIGH-Z",
>+				0,
>+				"External Reset",
>+				"1.2V supply below 0.7V",
>+				"HP regulator's LVD",
>+				"ULP regulator's LVD",
>+				"3.3V main supply is unstable",
>+				"LP regulator's LVD",
>+				0,
>+				0,
>+				0,
>+				"MDM-AP system reset request is set",
>+				"Hard Fail State of System Security Monitor",
>+				"SRC_SCR SW Reset is set",
>+				"Platform's CSU alarm event",
>+				0,
>+				0,
>+				0,
>+				0,
>+				"Anadig regulator 1.1V unstable",
>+				"Anadig regulator 2.5V unstable",
>+				"Anadig regulator 3.0V unstable",
>+				"CMU even when FOSC freq less than 40MHz",
>+				"CMU event when BUS freq is out of range",
>+				"No clock is detected on FOSC",
>+				"No clock is detected on SOSC",
>+				"CM4 is in lockup"};
>+	u32 cause;
>+	int i, bit;
>+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
>+
>+	cause = readl(&src_regs->srsr);
>+	writel(cause, &src_regs->srsr);
>+
>+	for (i = 0; i < 32; i++) {
>+		bit = 1 << i;
>+		if ((cause & bit) == bit) {
>+			if (resetcause[i] != NULL)
>+				return resetcause[i];
>+		}
>+	}
>+
>+	return 0;
>+}
>+
>+#if defined(CONFIG_DISPLAY_CPUINFO)
>+int print_cpuinfo(void)
>+{
>+	u32 cpurev;
>+
>+	cpurev = get_cpu_rev();
>+	printf("CPU:   Freescale VyBrid %x family rev%d.%d at %d MHz\n",
>+		(cpurev & 0xFFF000) >> 12,
>+		(cpurev & 0x000F0) >> 4,
>+		(cpurev & 0x0000F) >> 0,
>+		vybrid_get_clock(VYBRID_ARM_CLK) / 1000000);
>+	printf("Reset cause: %s\n", get_reset_cause());
>+	return 0;
>+}
>+#endif
>+
>+int cpu_eth_init(bd_t *bis)
>+{
>+	int rc = -ENODEV;
>+
>+	rc = mcffec_initialize(bis);
>+
>+	return rc;
>+}
>+
>+/* Initializes on-chip MMC controllers.
>+ * to override, implement board_mmc_init()
>+ */
>+int cpu_mmc_init(bd_t *bis)
>+{
>+#ifdef CONFIG_FSL_ESDHC
>+	return fsl_esdhc_mmc_init(bis);
>+#else
>+	return 0;
>+#endif
>+}
>+
>+void reset_cpu(ulong addr)
>+{
>+	__raw_writew(4, WDOG_A5_BASE_ADDR);
>+}
>diff --git a/arch/arm/cpu/armv7/vybrid-common/speed.c
>b/arch/arm/cpu/armv7/vybrid-common/speed.c
>new file mode 100644
>index 0000000..3be85ea
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid-common/speed.c
>@@ -0,0 +1,37 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <common.h>
>+#include <asm/arch/clock.h>
>+
>+DECLARE_GLOBAL_DATA_PTR;
>+
>+int get_clocks(void)
>+{
>+	gd->bus_clk = vybrid_get_clock(VYBRID_BUS_CLK);
>+	gd->arch.ipg_clk = vybrid_get_clock(VYBRID_IPG_CLK);
>+
>+#ifdef CONFIG_FSL_ESDHC
>+	gd->arch.sdhc_clk = vybrid_get_clock(VYBRID_SDHC_CLK);
>+#endif
>+	return 0;
>+}
>diff --git a/arch/arm/cpu/armv7/vybrid-common/timer.c
>b/arch/arm/cpu/armv7/vybrid-common/timer.c
>new file mode 100644
>index 0000000..be990e6
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid-common/timer.c
>@@ -0,0 +1,140 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <common.h>
>+#include <asm/io.h>
>+#include <div64.h>
>+#include <asm/arch/timer.h>
>+#include <asm/arch/clock.h>
>+#include <asm/arch/vybrid-regs.h>
>+
>+DECLARE_GLOBAL_DATA_PTR;
>+
>+#define timestamp (gd->arch.tbl)
>+#define timerticks (gd->arch.tbu)
>+#define lastinc	(gd->arch.lastinc)
>+static unsigned long ltmstamp;
>+
>+#define CONFIG_TMR_USEPIT
>+#ifdef CONFIG_TMR_USEPIT
>+

The only timer here you are using in the code is the PIT and you did not 
Provide the code to support the flex timer, so I suggest remove the above
Code.
 
>+int timer_init(void)
>+{
>+	ulong usecs;
>+	ulong ticks;
>+
>+	timestamp = 0;
>+
>+	/*
>+	 * nsecs conversion = (1/ipg_clk) * 10^9
>+	 * equivalent to 1000 / (ipg_clk / 10^6)
>+	 */
>+	usecs = (vybrid_get_clock(VYBRID_IPG_CLK) / 1000000);
             ^                                            ^
Do you need the parentheses as above?

>+	ticks = 1000 / usecs;
>+
>+	clrbits_le32(PIT_MCR, 2);	/* enable PIT */
>+
>+	/* ticks per 10 us = 10000 us / usecs = cycles time */
>+	timerticks = (10 * 1000) / ticks;
>+
>+	__raw_writel(0xFFFFFFFF, PIT_LDVAL1);
>+	__raw_writel(0, PIT_TCTRL1);
>+	__raw_writel(4, PIT_TCTRL1);
>+	__raw_writel(5, PIT_TCTRL1);
>+	__raw_writel(timerticks, PIT_LDVAL0);
>+	__raw_writel(1, PIT_TCTRL0);
>+
>+	lastinc = __raw_readl(PIT_LTMR64H);
>+
>+	return 0;
>+}
>+
>+ulong get_timer(ulong base)
>+{
>+	unsigned long now, diff;
>+
>+	now = __raw_readl(PIT_LTMR64H);
>+	diff = -(now - lastinc);
>+	ltmstamp += diff;
>+	while (ltmstamp > 100) {
>+		timestamp++;
>+		ltmstamp -= 100;
>+	}
>+	lastinc = now;
>+
>+	return timestamp - base;
>+}
>+
>+/* delay x useconds AND preserve advance timstamp value */
>+void __udelay(unsigned long usec)
>+{
>+	ulong nsecs, tmp;
>+
>+	/*
>+	 * nsecs conversion = (1/ipg_clk) * 10^9
>+	 * equivalent to 1000 / (ipg_clk / 10^6)
>+	 */
>+	if (usec < 5)
>+		usec = 10;
>+
>+	nsecs = gd->arch.ipg_clk / 1000000;
>+	nsecs = 1000 / nsecs;
>+
>+	/* 1 us per ticks = 1000 ns / nsecs = cycles time */
>+	while (usec > 0) {
>+		if (usec > 65000)
>+			tmp = 65000;
>+		else
>+			tmp = usec;
>+		usec = usec - tmp;
>+
>+		tmp =  (tmp * 1000) / nsecs;
>+
>+		__raw_writel(tmp, PIT_LDVAL2);
>+		__raw_writel(1, PIT_TCTRL2);
>+
>+		while ((__raw_readl(PIT_TFLG2) & 1) != 1)
>+			;
>+		__raw_writel(0, PIT_TCTRL2);
>+		__raw_writel(1, PIT_TFLG2);
>+	}

u-boot upstream recommend that we use the structure access not the base + offset,
please consider to change to the u-boot upstream style. 

For example, we have the following code in the imx:

i = __raw_readl(&cur_gpt->control);
__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);

>+}
>+#endif			/* CONFIG_TMR_USEPIT */
>+
>+/*
>+ * This function is derived from PowerPC code (timebase clock
>frequency).
>+ * On ARM it returns the number of timer ticks per second.
>+ */
>+unsigned long long _usec2ticks(unsigned long long usec)
>+{
>+	return usec;
>+}
>+
>+unsigned long long get_ticks(void)
>+{
>+	return get_timer(0);
>+}
>+
>+ulong get_tbclk(void)
>+{
>+	return CONFIG_SYS_HZ;
>+}
>diff --git a/arch/arm/cpu/armv7/vybrid/Makefile
>b/arch/arm/cpu/armv7/vybrid/Makefile
>new file mode 100644
>index 0000000..f71e3fb
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid/Makefile
>@@ -0,0 +1,45 @@
>+#
>+# Copyright 2012-2013 Freescale Semiconductor, Inc.
>+#
>+# See file CREDITS for list of people who contributed to this
>+# project.
>+#
>+# This program is free software; you can redistribute it and/or
>+# modify it under the terms of the GNU General Public License as
>+# published by the Free Software Foundation; either version 2 of
>+# the License, or (at your option) any later version.
>+#
>+# This program is distributed in the hope that it will be useful,
>+# but WITHOUT ANY WARRANTY; without even the implied warranty of
>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+# GNU General Public License for more details.
>+#
>+# You should have received a copy of the GNU General Public License
>+# along with this program; if not, write to the Free Software
>+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+# MA 02111-1307 USA
>+#
>+
>+include $(TOPDIR)/config.mk
>+
>+LIB	= $(obj)lib$(SOC).o
>+
>+COBJS	= soc.o clock.o iomux.o
>+SOBJS = lowlevel_init.o
>+
>+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
>+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
>+
>+all:	$(obj).depend $(LIB)
>+
>+$(LIB):	$(OBJS)
>+	$(call cmd_link_o_target, $(OBJS))
>+
>+#######################################################################
>##
>+
>+# defines $(obj).depend target
>+include $(SRCTREE)/rules.mk
>+
>+sinclude $(obj).depend
>+
>+#######################################################################
>##
>diff --git a/arch/arm/cpu/armv7/vybrid/asm-offsets.c
>b/arch/arm/cpu/armv7/vybrid/asm-offsets.c
>new file mode 100644
>index 0000000..2951f78
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid/asm-offsets.c
>@@ -0,0 +1,70 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
>+ *
>+ * This program is used to generate definitions needed by
>+ * assembly language modules.
>+ *
>+ * We use the technique used in the OSF Mach kernel code:
>+ * generate asm statements containing #defines,
>+ * compile this file to assembler, and then extract the
>+ * #defines from the assembly-language output.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License
>+ * as published by the Free Software Foundation; either version
>+ * 2 of the License, or (at your option) any later version.
>+ */
>+
>+#include <common.h>
>+#include <asm/arch/vybrid-regs.h>
>+
>+#include <linux/kbuild.h>
>+
>+int main(void)
>+{
>+	/* Round up to make sure size gives nice stack alignment */
>+	DEFINE(CLKCTL_CCR, offsetof(struct clkctl, ccr));
>+	DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
>+	DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
>+	DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
>+	DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
>+	DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
>+	DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
>+	DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
>+	DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
>+	DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
>+	DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
>+	DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
>+	DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
>+	DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
>+	DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
>+
>+	DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
>+	DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
>+	DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
>+	DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
>+	DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
>+	DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
>+	DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
>+	DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
>+	DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
>+	DEFINE(CLKCTL_CCGR8, offsetof(struct clkctl, ccgr8));
>+	DEFINE(CLKCTL_CCGR9, offsetof(struct clkctl, ccgr9));
>+	DEFINE(CLKCTL_CCGR10, offsetof(struct clkctl, ccgr10));
>+	DEFINE(CLKCTL_CCGR11, offsetof(struct clkctl, ccgr11));
>+	DEFINE(CLKCTL_CMEOR0, offsetof(struct clkctl, cmeor0));
>+	DEFINE(CLKCTL_CMEOR1, offsetof(struct clkctl, cmeor1));
>+	DEFINE(CLKCTL_CMEOR2, offsetof(struct clkctl, cmeor2));
>+	DEFINE(CLKCTL_CMEOR3, offsetof(struct clkctl, cmeor3));
>+	DEFINE(CLKCTL_CMEOR4, offsetof(struct clkctl, cmeor4));
>+	DEFINE(CLKCTL_CMEOR5, offsetof(struct clkctl, cmeor5));
>+	DEFINE(CLKCTL_CPPDSR, offsetof(struct clkctl, cppdsr));
>+	DEFINE(CLKCTL_CCOWR, offsetof(struct clkctl, ccowr));
>+	DEFINE(CLKCTL_CCPGR0, offsetof(struct clkctl, ccpgr0));
>+	DEFINE(CLKCTL_CCPGR1, offsetof(struct clkctl, ccpgr1));
>+	DEFINE(CLKCTL_CCPGR2, offsetof(struct clkctl, ccpgr2));
>+	DEFINE(CLKCTL_CCPGR3, offsetof(struct clkctl, ccpgr3));
>+
>+	return 0;
>+}
>diff --git a/arch/arm/cpu/armv7/vybrid/clock.c
>b/arch/arm/cpu/armv7/vybrid/clock.c
>new file mode 100644
>index 0000000..073b949
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid/clock.c
>@@ -0,0 +1,278 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <common.h>
>+#include <asm/io.h>
>+#include <asm/errno.h>
>+#include <asm/arch/vybrid-regs.h>
>+#include <asm/arch/clock.h>
>+#include <div64.h>
>+
>+DECLARE_GLOBAL_DATA_PTR;
>+
>+enum pll_clocks {
>+	PLL1_CLOCK = 0,
>+	PLL2_CLOCK,
>+	PLL3_CLOCK,
>+	PLL4_CLOCK,
>+	PLL_CLOCKS,
>+};
>+
>+struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
>+
>+/* Get mcu main rate */
>+static u32 get_mcu_main_clk(void)
>+{
>+	struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
>+	u32 ccm_ccsr, ccm_cacrr, armclk_div;
>+	u32 sysclk_sel, pll_pfd_sel = 0;
>+	u32 freq = 0;
>+
>+	ccm_ccsr = readl(&ccm->ccsr);
>+	sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
>+	sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
>+
>+	ccm_cacrr = readl(&ccm->cacrr);
>+	armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
>+	armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
>+	armclk_div += 1;
>+
>+	switch (sysclk_sel) {
>+	case 0:
>+		freq = FASE_CLK_FREQ;
>+		break;
>+	case 1:
>+		freq = SLOW_CLK_FREQ;
>+		break;
>+	case 3:
>+		freq = PLL2_MAIN_FREQ;
>+		break;
>+	case 5:
>+		freq = PLL3_MAIN_FREQ;
>+		break;
>+	case 2:
>+		pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
>+		pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
>+		break;
>+	case 4:
>+		pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
>+		pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
>+		break;
>+	default:
>+		printf("unsupported system clock select\n");
>+	}
>+
>+	if (sysclk_sel == 2) {
>+		switch (pll_pfd_sel) {
>+		case 0:
>+			freq = PLL2_MAIN_FREQ;
>+			break;
>+		case 1:
>+			freq = PLL2_PFD1_FREQ;
>+			break;
>+		case 2:
>+			freq = PLL2_PFD2_FREQ;
>+			break;
>+		case 3:
>+			freq = PLL2_PFD3_FREQ;
>+			break;
>+		case 4:
>+			freq = PLL2_PFD4_FREQ;
>+			break;
>+		default:
>+			break;
>+		}
>+	} else if (sysclk_sel == 4) {
>+		switch (pll_pfd_sel) {
>+		case 0:
>+			freq = PLL1_MAIN_FREQ;
>+			break;
>+		case 1:
>+			freq = PLL1_PFD1_FREQ;
>+			break;
>+		case 2:
>+			freq = PLL1_PFD2_FREQ;
>+			break;
>+		case 3:
>+			freq = PLL1_PFD3_FREQ;
>+			break;
>+		case 4:
>+			freq = PLL1_PFD4_FREQ;
>+			break;
>+		default:
>+			break;
>+		}
>+	}
>+
>+	return freq / armclk_div;
>+}
>+
>+/* Get the rate of bus clock */
>+static u32 get_bus_clk(void)
>+{
>+	struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
>+	u32 ccm_cacrr, busclk_div;
>+
>+	ccm_cacrr = readl(&ccm->cacrr);
>+
>+	busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
>+	busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
>+	busclk_div += 1;
>+
>+	return get_mcu_main_clk() / busclk_div;
>+}
>+
>+/* Get the rate of ipg clock */
>+static u32 get_ipg_clk(void)
>+{
>+	struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
>+	u32 ccm_cacrr, ipgclk_div;
>+
>+	ccm_cacrr = readl(&ccm->cacrr);
>+
>+	ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
>+	ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
>+	ipgclk_div += 1;
>+
>+	return get_bus_clk() / ipgclk_div;
>+}
>+
>+/* get dspi clock rate */
>+static u32 vybrid_get_dspiclk(void)
>+{
>+	return get_ipg_clk();
>+}
>+
>+/* The API of get vybrid clocks */
>+unsigned int vybrid_get_clock(enum vybrid_clock clk)
>+{
>+	switch (clk) {
>+	case VYBRID_ARM_CLK:
>+		return get_mcu_main_clk();
>+	case VYBRID_BUS_CLK:
>+		return get_bus_clk();
>+	case VYBRID_IPG_CLK:
>+		return get_ipg_clk();
>+	case VYBRID_UART_CLK:
>+		return vybrid_get_uartclk();
>+	case VYBRID_DSPI_CLK:
>+		return vybrid_get_dspiclk();
>+	case VYBRID_SDHC_CLK:
>+		return vybrid_get_sdhcclk();
>+	case VYBRID_FEC_CLK:
>+		return vybrid_get_fecclk();
>+	default:
>+		break;
>+	}
>+	return -1;
>+}
>+
>+/* Get the rate of uart clk */
>+u32 vybrid_get_uartclk(void)
>+{
>+	return get_ipg_clk();
>+}
>+
>+/* Get the rate of uart clk */
>+u32 vybrid_get_sdhcclk(void)
>+{
>+	struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
>+	u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
>+	u32 freq = 0;
>+
>+	ccm_cscmr1 = readl(&ccm->cscmr1);
>+	sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
>+	sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
>+
>+	ccm_cscdr2 = readl(&ccm->cscdr2);
>+	sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
>+	sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
>+	sdhc_clk_div += 1;
>+
>+	switch (sdhc_clk_sel) {
>+	case 0:
>+		freq = PLL3_MAIN_FREQ;
>+		break;
>+	case 1:
>+		freq = PLL3_PFD3_FREQ;
>+		break;
>+	case 2:
>+		freq = PLL1_PFD3_FREQ;
>+		break;
>+	case 3:
>+		freq = get_bus_clk();
>+		break;
>+	}
>+
>+	return freq / sdhc_clk_div;
>+}
>+
>+u32 vybrid_get_fecclk(void)
>+{
>+	struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
>+	u32 ccm_cscmr2, rmii_clk_sel;
>+	u32 freq = 0;
>+
>+	ccm_cscmr2 = readl(&ccm->cscmr2);
>+	rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
>+	rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
>+
>+	switch (rmii_clk_sel) {
>+	case 0:
>+		freq = ENET_EXTERNAL_CLK;
>+		break;
>+	case 1:
>+		freq = AUDIO_EXTERNAL_CLK;
>+		break;
>+	case 2:
>+		freq = PLL5_MAIN_FREQ;
>+		break;
>+	case 3:
>+		freq = PLL5_MAIN_FREQ / 2;
>+		break;
>+	}
>+
>+	return freq;
>+}
>+
>+/* Dump some core clocks */
>+int do_vybrid_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
>+			 char * const argv[])
>+{
>+	printf("\n");
>+	printf("ARM        %8d kHz\n",
>+		vybrid_get_clock(VYBRID_ARM_CLK) / 1000);
>+	printf("BUS        %8d kHz\n",
>+		vybrid_get_clock(VYBRID_BUS_CLK) / 1000);
>+	printf("IPG        %8d kHz\n",
>+		vybrid_get_clock(VYBRID_IPG_CLK) / 1000);
>+
>+	return 0;
>+}
>+
>+/***************************************************/
>+
>+U_BOOT_CMD(
>+	clocks,	CONFIG_SYS_MAXARGS, 1, do_vybrid_showclocks,
>+	"display clocks",
>+	""
>+);
>diff --git a/arch/arm/cpu/armv7/vybrid/iomux.c
>b/arch/arm/cpu/armv7/vybrid/iomux.c
>new file mode 100644
>index 0000000..fb672e3
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid/iomux.c
>@@ -0,0 +1,42 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <common.h>
>+#include <asm/io.h>
>+#include <asm/arch/vybrid-regs.h>
>+#include <asm/arch/vybrid-pins.h>
>+#include <asm/arch/iomux.h>
>+#include <asm/arch/sys_proto.h>
>+
>+void pad_iomux_set(u32 pad_addr, struct pad_iomux *padio)
>+{
>+	u32 value;
>+
>+	value = (((padio->mod & 7) << 20) | ((padio->spd & 3) << 12) |
>	\
>+		 ((padio->sre & 1) << 11) | ((padio->ode & 1) << 10) |
>	\
>+		 ((padio->hys & 1) << 9) | ((padio->dse & 7) << 6) |	\
>+		 ((padio->pus & 3) << 4) | ((padio->pke & 1) << 3) |	\
>+		 ((padio->pue & 1) << 2) | ((padio->obe & 1) << 1) |	\
>+		 ((padio->ibe & 1) << 0));
>+
>+	__raw_writel(pad_addr, value);

Is this correct? __raw_writel should be (v, a), but you are opposite?

>+}
>diff --git a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
>b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
>new file mode 100644
>index 0000000..c2bda4f
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
>@@ -0,0 +1,128 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <config.h>
>+#include <asm/arch/vybrid-regs.h>
>+#include <generated/asm-offsets.h>
>+
>+/* DDR */
>+.macro  init_drive_strength
>+.endm /* init_drive_strength */
>+
>+.macro setup_pll pll, freq
>+.endm
>+
>+.macro init_clock
>+	ldr r0, =CCM_BASE_ADDR
>+
>+	ldr r1, =CONFIG_SYS_CLKCTRL_CLPCR
>+	str r1, [r0, #CLKCTL_CLPCR]
>+
>+	/* Gate of clocks to the peripherals first */
>+	ldr r1, =CONFIG_SYS_CLKCTL_CCGR0
>+	str r1, [r0, #CLKCTL_CCGR0]
>+	ldr r1, =CONFIG_SYS_CLKCTL_CCGR1
>+	str r1, [r0, #CLKCTL_CCGR1]
>+	ldr r1, =CONFIG_SYS_CLKCTL_CCGR2
>+	str r1, [r0, #CLKCTL_CCGR2]
>+	ldr r1, =CONFIG_SYS_CLKCTL_CCGR3
>+	str r1, [r0, #CLKCTL_CCGR3]
>+	ldr r1, =CONFIG_SYS_CLKCTL_CCGR4
>+	str r1, [r0, #CLKCTL_CCGR4]
>+	ldr r1, =CONFIG_SYS_CLKCTL_CCGR5
>+	str r1, [r0, #CLKCTL_CCGR5]
>+	ldr r1, =CONFIG_SYS_CLKCTL_CCGR6
>+	str r1, [r0, #CLKCTL_CCGR6]
>+	ldr r1, =CONFIG_SYS_CLKCTL_CCGR7
>+	str r1, [r0, #CLKCTL_CCGR7]
>+	ldr r1, =CONFIG_SYS_CLKCTL_CCGR8
>+	str r1, [r0, #CLKCTL_CCGR8]
>+	ldr r1, =CONFIG_SYS_CLKCTL_CCGR9
>+	str r1, [r0, #CLKCTL_CCGR9]
>+	ldr r1, =CONFIG_SYS_CLKCTL_CCGR10
>+	str r1, [r0, #CLKCTL_CCGR10]
>+	ldr r1, =CONFIG_SYS_CLKCTL_CCGR11
>+	str r1, [r0, #CLKCTL_CCGR11]
>+
>+	ldr r2, =ANATOP_BASE_ADDR
>+	ldr r1, =CONFIG_SYS_ANADIG_528_CTRL
>+	str r1, [r2, #0x30]
>+	ldr r1, =CONFIG_SYS_ANADIG_ENET_CTRL
>+	str r1, [r2, #0xE0]
>+	ldr r1, =CONFIG_SYS_ANADIG_SYS_CTRL
>+	str r1, [r2, #0x270]
>+	/* check for lock */
>+
>+	ldr r1, =CONFIG_SYS_CLKCTRL_CCR
>+	str r1, [r0, #CLKCTL_CCR]
>+
>+	ldr r1, =CONFIG_SYS_CLKCTRL_CCSR
>+	str r1, [r0, #CLKCTL_CCSR]
>+
>+	ldr r1, =CONFIG_SYS_CLKCTRL_CACRR
>+	str r1, [r0, #CLKCTL_CACRR]
>+
>+	ldr r1, =CONFIG_SYS_CLKCTRL_CSCMR1
>+	str r1, [r0, #CLKCTL_CSCMR1]
>+
>+	ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR1
>+	str r1, [r0, #CLKCTL_CSCDR1]
>+
>+	ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR2
>+	str r1, [r0, #CLKCTL_CSCDR2]
>+
>+	ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR3
>+	str r1, [r0, #CLKCTL_CSCDR3]
>+
>+	ldr r1, =CONFIG_SYS_CLKCTRL_CSCMR2
>+	str r1, [r0, #CLKCTL_CSCMR2]
>+
>+	ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR4
>+	str r1, [r0, #CLKCTL_CSCDR4]
>+.endm
>+
>+.macro setup_wdog
>+	ldr r0, =WDOG_A5_BASE_ADDR
>+	mov r1, #0x30
>+	strh r1, [r0]
>+.endm

What the code does here, disable-wdog, right? 
IMHO, 
- We can't disable the WDG if it already enabled.
- The macro name, setup_wdog will confuse others, since the reader may guess
   Will setup(enable) the WDG. 

But I guess this code is useless, you can remove it. 

>+
>+.section ".text.init", "x"
>+
>+.globl lowlevel_init
>+lowlevel_init:
>+	/* ARM errata ID #468414 */
>+	mrc 15, 0, r1, c1, c0, 1
>+	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
>+	mcr 15, 0, r1, c1, c0, 1
>+

Does this errata applied to A5 too?

>+#ifndef CONFIG_SYS_BOOTHDR
>+	init_clock
>+#endif
>+
>+	/* r12 saved upper lr*/
>+	mov pc,lr
>+
>+/* Board level setting value */
>+DDR_PERCHARGE_CMD:	.word 0x04008008
>+DDR_REFRESH_CMD:	.word 0x00008010
>+DDR_LMR1_W:		.word 0x00338018
>+DDR_LMR_CMD:		.word 0xB2220000
>+DDR_TIMING_W:		.word 0xB02567A9
>+DDR_MISC_W:		.word 0x000A0104
>diff --git a/arch/arm/cpu/armv7/vybrid/soc.c
>b/arch/arm/cpu/armv7/vybrid/soc.c
>new file mode 100644
>index 0000000..e73d6c4
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid/soc.c
>@@ -0,0 +1,42 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <common.h>
>+#include <asm/arch/vybrid-regs.h>
>+#include <asm/arch/clock.h>
>+#include <asm/arch/sys_proto.h>
>+
>+#include <asm/errno.h>
>+#include <asm/io.h>
>+
>+#if !(defined(CONFIG_VYBRID))
>+#error "CPU_TYPE not defined"
>+#endif
>+
>+u32 get_cpu_rev(void)
>+{
>+	int system_rev = 0x600000;

What's the hard code 0x600000 means?

>+	int reg = __raw_readl(ROM_SI_REV);
>+
>+	system_rev |= reg;
>+	return system_rev;
>+}
>diff --git a/arch/arm/include/asm/arch-vybrid/clock.h
>b/arch/arm/include/asm/arch-vybrid/clock.h
>new file mode 100644
>index 0000000..bf95b13
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-vybrid/clock.h
>@@ -0,0 +1,41 @@
>+/*
>+ * Copyright 2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#ifndef __ASM_ARCH_CLOCK_H
>+#define __ASM_ARCH_CLOCK_H
>+
>+enum vybrid_clock {
>+	VYBRID_ARM_CLK = 0,
>+	VYBRID_BUS_CLK,
>+	VYBRID_IPG_CLK,
>+	VYBRID_UART_CLK,
>+	VYBRID_DSPI_CLK,
>+	VYBRID_SDHC_CLK,
>+	VYBRID_FEC_CLK,
>+};
>+
>+u32 vybrid_get_uartclk(void);
>+u32 vybrid_get_sdhcclk(void);
>+u32 vybrid_get_fecclk(void);
>+unsigned int vybrid_get_clock(enum vybrid_clock clk);
>+
>+#endif /* __ASM_ARCH_CLOCK_H */
>diff --git a/arch/arm/include/asm/arch-vybrid/iomux.h
>b/arch/arm/include/asm/arch-vybrid/iomux.h
>new file mode 100644
>index 0000000..94f8b0b
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-vybrid/iomux.h
>@@ -0,0 +1,323 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#ifndef __MACH_VYBRID_IOMUX_H__
>+#define __MACH_VYBRID_IOMUX_H__
>+
>+#include <common.h>
>+#include <asm/io.h>
>+#include <asm/arch/vybrid-regs.h>
>+#include <asm/arch/vybrid-pins.h>
>+
>+#define IOMUXC_PAD_000		(IOMUXC_BASE_ADDR + 0x0000)
>+#define IOMUXC_PAD_001		(IOMUXC_BASE_ADDR + 0x0004)
>+#define IOMUXC_PAD_002		(IOMUXC_BASE_ADDR + 0x0008)
>+#define IOMUXC_PAD_003		(IOMUXC_BASE_ADDR + 0x000C)
>+#define IOMUXC_PAD_004		(IOMUXC_BASE_ADDR + 0x0010)
>+#define IOMUXC_PAD_005		(IOMUXC_BASE_ADDR + 0x0014)
>+#define IOMUXC_PAD_006		(IOMUXC_BASE_ADDR + 0x0018)
>+#define IOMUXC_PAD_007		(IOMUXC_BASE_ADDR + 0x001C)
>+#define IOMUXC_PAD_008		(IOMUXC_BASE_ADDR + 0x0020)
>+#define IOMUXC_PAD_009		(IOMUXC_BASE_ADDR + 0x0024)
>+#define IOMUXC_PAD_010		(IOMUXC_BASE_ADDR + 0x0028)
>+#define IOMUXC_PAD_011		(IOMUXC_BASE_ADDR + 0x002C)
>+#define IOMUXC_PAD_012		(IOMUXC_BASE_ADDR + 0x0030)
>+#define IOMUXC_PAD_013		(IOMUXC_BASE_ADDR + 0x0034)
>+#define IOMUXC_PAD_014		(IOMUXC_BASE_ADDR + 0x0038)
>+#define IOMUXC_PAD_015		(IOMUXC_BASE_ADDR + 0x003C)
>+#define IOMUXC_PAD_016		(IOMUXC_BASE_ADDR + 0x0040)
>+#define IOMUXC_PAD_017		(IOMUXC_BASE_ADDR + 0x0044)
>+#define IOMUXC_PAD_018		(IOMUXC_BASE_ADDR + 0x0048)
>+#define IOMUXC_PAD_019		(IOMUXC_BASE_ADDR + 0x004C)
>+#define IOMUXC_PAD_020		(IOMUXC_BASE_ADDR + 0x0050)
>+#define IOMUXC_PAD_021		(IOMUXC_BASE_ADDR + 0x0054)
>+#define IOMUXC_PAD_022		(IOMUXC_BASE_ADDR + 0x0058)
>+#define IOMUXC_PAD_023		(IOMUXC_BASE_ADDR + 0x005C)
>+#define IOMUXC_PAD_024		(IOMUXC_BASE_ADDR + 0x0060)
>+#define IOMUXC_PAD_025		(IOMUXC_BASE_ADDR + 0x0064)
>+#define IOMUXC_PAD_026		(IOMUXC_BASE_ADDR + 0x0068)
>+#define IOMUXC_PAD_027		(IOMUXC_BASE_ADDR + 0x006C)
>+#define IOMUXC_PAD_028		(IOMUXC_BASE_ADDR + 0x0070)
>+#define IOMUXC_PAD_029		(IOMUXC_BASE_ADDR + 0x0074)
>+#define IOMUXC_PAD_030		(IOMUXC_BASE_ADDR + 0x0078)
>+#define IOMUXC_PAD_031		(IOMUXC_BASE_ADDR + 0x007C)
>+#define IOMUXC_PAD_032		(IOMUXC_BASE_ADDR + 0x0080)
>+#define IOMUXC_PAD_033		(IOMUXC_BASE_ADDR + 0x0084)
>+#define IOMUXC_PAD_034		(IOMUXC_BASE_ADDR + 0x0088)
>+#define IOMUXC_PAD_035		(IOMUXC_BASE_ADDR + 0x008C)
>+#define IOMUXC_PAD_036		(IOMUXC_BASE_ADDR + 0x0090)
>+#define IOMUXC_PAD_037		(IOMUXC_BASE_ADDR + 0x0094)
>+#define IOMUXC_PAD_038		(IOMUXC_BASE_ADDR + 0x0098)
>+#define IOMUXC_PAD_039		(IOMUXC_BASE_ADDR + 0x009C)
>+#define IOMUXC_PAD_040		(IOMUXC_BASE_ADDR + 0x00A0)
>+#define IOMUXC_PAD_041		(IOMUXC_BASE_ADDR + 0x00A4)
>+#define IOMUXC_PAD_042		(IOMUXC_BASE_ADDR + 0x00A8)
>+#define IOMUXC_PAD_043		(IOMUXC_BASE_ADDR + 0x00AC)
>+#define IOMUXC_PAD_044		(IOMUXC_BASE_ADDR + 0x00B0)
>+#define IOMUXC_PAD_045		(IOMUXC_BASE_ADDR + 0x00B4)
>+#define IOMUXC_PAD_046		(IOMUXC_BASE_ADDR + 0x00B8)
>+#define IOMUXC_PAD_047		(IOMUXC_BASE_ADDR + 0x00BC)
>+#define IOMUXC_PAD_048		(IOMUXC_BASE_ADDR + 0x00C0)
>+#define IOMUXC_PAD_049		(IOMUXC_BASE_ADDR + 0x00C4)
>+#define IOMUXC_PAD_050		(IOMUXC_BASE_ADDR + 0x00C8)
>+#define IOMUXC_PAD_051		(IOMUXC_BASE_ADDR + 0x00CC)
>+#define IOMUXC_PAD_052		(IOMUXC_BASE_ADDR + 0x00D0)
>+#define IOMUXC_PAD_053		(IOMUXC_BASE_ADDR + 0x00D4)
>+#define IOMUXC_PAD_054		(IOMUXC_BASE_ADDR + 0x00D8)
>+#define IOMUXC_PAD_055		(IOMUXC_BASE_ADDR + 0x00DC)
>+#define IOMUXC_PAD_056		(IOMUXC_BASE_ADDR + 0x00E0)
>+#define IOMUXC_PAD_057		(IOMUXC_BASE_ADDR + 0x00E4)
>+#define IOMUXC_PAD_058		(IOMUXC_BASE_ADDR + 0x00E8)
>+#define IOMUXC_PAD_059		(IOMUXC_BASE_ADDR + 0x00EC)
>+#define IOMUXC_PAD_060		(IOMUXC_BASE_ADDR + 0x00F0)
>+#define IOMUXC_PAD_061		(IOMUXC_BASE_ADDR + 0x00F4)
>+#define IOMUXC_PAD_062		(IOMUXC_BASE_ADDR + 0x00F8)
>+#define IOMUXC_PAD_063		(IOMUXC_BASE_ADDR + 0x00FC)
>+#define IOMUXC_PAD_064		(IOMUXC_BASE_ADDR + 0x0100)
>+#define IOMUXC_PAD_065		(IOMUXC_BASE_ADDR + 0x0104)
>+#define IOMUXC_PAD_066		(IOMUXC_BASE_ADDR + 0x0108)
>+#define IOMUXC_PAD_067		(IOMUXC_BASE_ADDR + 0x010C)
>+#define IOMUXC_PAD_068		(IOMUXC_BASE_ADDR + 0x0110)
>+#define IOMUXC_PAD_069		(IOMUXC_BASE_ADDR + 0x0114)
>+#define IOMUXC_PAD_070		(IOMUXC_BASE_ADDR + 0x0118)
>+#define IOMUXC_PAD_071		(IOMUXC_BASE_ADDR + 0x011C)
>+#define IOMUXC_PAD_072		(IOMUXC_BASE_ADDR + 0x0120)
>+#define IOMUXC_PAD_073		(IOMUXC_BASE_ADDR + 0x0124)
>+#define IOMUXC_PAD_074		(IOMUXC_BASE_ADDR + 0x0128)
>+#define IOMUXC_PAD_075		(IOMUXC_BASE_ADDR + 0x012C)
>+#define IOMUXC_PAD_076		(IOMUXC_BASE_ADDR + 0x0130)
>+#define IOMUXC_PAD_077		(IOMUXC_BASE_ADDR + 0x0134)
>+#define IOMUXC_PAD_078		(IOMUXC_BASE_ADDR + 0x0138)
>+#define IOMUXC_PAD_079		(IOMUXC_BASE_ADDR + 0x013C)
>+#define IOMUXC_PAD_080		(IOMUXC_BASE_ADDR + 0x0140)
>+#define IOMUXC_PAD_081		(IOMUXC_BASE_ADDR + 0x0144)
>+#define IOMUXC_PAD_082		(IOMUXC_BASE_ADDR + 0x0148)
>+#define IOMUXC_PAD_083		(IOMUXC_BASE_ADDR + 0x014C)
>+#define IOMUXC_PAD_084		(IOMUXC_BASE_ADDR + 0x0150)
>+#define IOMUXC_PAD_085		(IOMUXC_BASE_ADDR + 0x0154)
>+#define IOMUXC_PAD_086		(IOMUXC_BASE_ADDR + 0x0158)
>+#define IOMUXC_PAD_087		(IOMUXC_BASE_ADDR + 0x015C)
>+#define IOMUXC_PAD_088		(IOMUXC_BASE_ADDR + 0x0160)
>+#define IOMUXC_PAD_089		(IOMUXC_BASE_ADDR + 0x0164)
>+#define IOMUXC_PAD_090		(IOMUXC_BASE_ADDR + 0x0168)
>+#define IOMUXC_PAD_091		(IOMUXC_BASE_ADDR + 0x016C)
>+#define IOMUXC_PAD_092		(IOMUXC_BASE_ADDR + 0x0170)
>+#define IOMUXC_PAD_093		(IOMUXC_BASE_ADDR + 0x0174)
>+#define IOMUXC_PAD_094		(IOMUXC_BASE_ADDR + 0x0178)
>+#define IOMUXC_PAD_095		(IOMUXC_BASE_ADDR + 0x017C)
>+#define IOMUXC_PAD_096		(IOMUXC_BASE_ADDR + 0x0180)
>+#define IOMUXC_PAD_097		(IOMUXC_BASE_ADDR + 0x0184)
>+#define IOMUXC_PAD_098		(IOMUXC_BASE_ADDR + 0x0188)
>+#define IOMUXC_PAD_099		(IOMUXC_BASE_ADDR + 0x018C)
>+#define IOMUXC_PAD_100		(IOMUXC_BASE_ADDR + 0x0190)
>+#define IOMUXC_PAD_101		(IOMUXC_BASE_ADDR + 0x0194)
>+#define IOMUXC_PAD_102		(IOMUXC_BASE_ADDR + 0x0198)
>+#define IOMUXC_PAD_103		(IOMUXC_BASE_ADDR + 0x019C)
>+#define IOMUXC_PAD_104		(IOMUXC_BASE_ADDR + 0x01A0)
>+#define IOMUXC_PAD_105		(IOMUXC_BASE_ADDR + 0x01A4)
>+#define IOMUXC_PAD_106		(IOMUXC_BASE_ADDR + 0x01A8)
>+#define IOMUXC_PAD_107		(IOMUXC_BASE_ADDR + 0x01AC)
>+#define IOMUXC_PAD_108		(IOMUXC_BASE_ADDR + 0x01B0)
>+#define IOMUXC_PAD_109		(IOMUXC_BASE_ADDR + 0x01B4)
>+#define IOMUXC_PAD_110		(IOMUXC_BASE_ADDR + 0x01B8)
>+#define IOMUXC_PAD_111		(IOMUXC_BASE_ADDR + 0x01BC)
>+#define IOMUXC_PAD_112		(IOMUXC_BASE_ADDR + 0x01C0)
>+#define IOMUXC_PAD_113		(IOMUXC_BASE_ADDR + 0x01C4)
>+#define IOMUXC_PAD_114		(IOMUXC_BASE_ADDR + 0x01C8)
>+#define IOMUXC_PAD_115		(IOMUXC_BASE_ADDR + 0x01CC)
>+#define IOMUXC_PAD_116		(IOMUXC_BASE_ADDR + 0x01D0)
>+#define IOMUXC_PAD_117		(IOMUXC_BASE_ADDR + 0x01D4)
>+#define IOMUXC_PAD_118		(IOMUXC_BASE_ADDR + 0x01D8)
>+#define IOMUXC_PAD_119		(IOMUXC_BASE_ADDR + 0x01DC)
>+#define IOMUXC_PAD_120		(IOMUXC_BASE_ADDR + 0x01E0)
>+#define IOMUXC_PAD_121		(IOMUXC_BASE_ADDR + 0x01E4)
>+#define IOMUXC_PAD_122		(IOMUXC_BASE_ADDR + 0x01E8)
>+#define IOMUXC_PAD_123		(IOMUXC_BASE_ADDR + 0x01EC)
>+#define IOMUXC_PAD_124		(IOMUXC_BASE_ADDR + 0x01F0)
>+#define IOMUXC_PAD_125		(IOMUXC_BASE_ADDR + 0x01F4)
>+#define IOMUXC_PAD_126		(IOMUXC_BASE_ADDR + 0x01F8)
>+#define IOMUXC_PAD_127		(IOMUXC_BASE_ADDR + 0x01FC)
>+#define IOMUXC_PAD_128		(IOMUXC_BASE_ADDR + 0x0200)
>+#define IOMUXC_PAD_129		(IOMUXC_BASE_ADDR + 0x0204)
>+#define IOMUXC_PAD_130		(IOMUXC_BASE_ADDR + 0x0208)
>+#define IOMUXC_PAD_131		(IOMUXC_BASE_ADDR + 0x020C)
>+#define IOMUXC_PAD_132		(IOMUXC_BASE_ADDR + 0x0210)
>+#define IOMUXC_PAD_133		(IOMUXC_BASE_ADDR + 0x0214)
>+#define IOMUXC_PAD_134		(IOMUXC_BASE_ADDR + 0x0218)
>+
>+#define IOMUXC_DDR_RESET	(IOMUXC_BASE_ADDR + 0x021C)
>+#define IOMUXC_DDR_A15		(IOMUXC_BASE_ADDR + 0x0220)
>+#define IOMUXC_DDR_A14		(IOMUXC_BASE_ADDR + 0x0224)
>+#define IOMUXC_DDR_A13		(IOMUXC_BASE_ADDR + 0x0228)
>+#define IOMUXC_DDR_A12		(IOMUXC_BASE_ADDR + 0x022C)
>+#define IOMUXC_DDR_A11		(IOMUXC_BASE_ADDR + 0x0230)
>+#define IOMUXC_DDR_A10		(IOMUXC_BASE_ADDR + 0x0234)
>+#define IOMUXC_DDR_A9		(IOMUXC_BASE_ADDR + 0x0238)
>+#define IOMUXC_DDR_A8		(IOMUXC_BASE_ADDR + 0x023C)
>+#define IOMUXC_DDR_A7		(IOMUXC_BASE_ADDR + 0x0240)
>+#define IOMUXC_DDR_A6		(IOMUXC_BASE_ADDR + 0x0244)
>+#define IOMUXC_DDR_A5		(IOMUXC_BASE_ADDR + 0x0248)
>+#define IOMUXC_DDR_A4		(IOMUXC_BASE_ADDR + 0x024C)
>+#define IOMUXC_DDR_A3		(IOMUXC_BASE_ADDR + 0x0250)
>+#define IOMUXC_DDR_A2		(IOMUXC_BASE_ADDR + 0x0254)
>+#define IOMUXC_DDR_A1		(IOMUXC_BASE_ADDR + 0x0258)
>+#define IOMUXC_DDR_A0		(IOMUXC_BASE_ADDR + 0x025C)
>+
>+#define IOMUXC_DDR_BA2		(IOMUXC_BASE_ADDR + 0x0260)
>+#define IOMUXC_DDR_BA1		(IOMUXC_BASE_ADDR + 0x0264)
>+#define IOMUXC_DDR_BA0		(IOMUXC_BASE_ADDR + 0x0268)
>+
>+#define IOMUXC_DDR_CAS		(IOMUXC_BASE_ADDR + 0x026C)
>+
>+#define IOMUXC_DDR_CKE		(IOMUXC_BASE_ADDR + 0x0270)
>+
>+#define IOMUXC_DDR_CLK		(IOMUXC_BASE_ADDR + 0x0274)
>+
>+#define IOMUXC_DDR_CS		(IOMUXC_BASE_ADDR + 0x0278)
>+
>+#define IOMUXC_DDR_D15		(IOMUXC_BASE_ADDR + 0x027C)
>+#define IOMUXC_DDR_D14		(IOMUXC_BASE_ADDR + 0x0280)
>+#define IOMUXC_DDR_D13		(IOMUXC_BASE_ADDR + 0x0284)
>+#define IOMUXC_DDR_D12		(IOMUXC_BASE_ADDR + 0x0288)
>+#define IOMUXC_DDR_D11		(IOMUXC_BASE_ADDR + 0x028C)
>+#define IOMUXC_DDR_D10		(IOMUXC_BASE_ADDR + 0x0290)
>+#define IOMUXC_DDR_D9		(IOMUXC_BASE_ADDR + 0x0294)
>+#define IOMUXC_DDR_D8		(IOMUXC_BASE_ADDR + 0x0298)
>+#define IOMUXC_DDR_D7		(IOMUXC_BASE_ADDR + 0x029C)
>+#define IOMUXC_DDR_D6		(IOMUXC_BASE_ADDR + 0x02A0)
>+#define IOMUXC_DDR_D5		(IOMUXC_BASE_ADDR + 0x02A4)
>+#define IOMUXC_DDR_D4		(IOMUXC_BASE_ADDR + 0x02A8)
>+#define IOMUXC_DDR_D3		(IOMUXC_BASE_ADDR + 0x02AC)
>+#define IOMUXC_DDR_D2		(IOMUXC_BASE_ADDR + 0x02B0)
>+#define IOMUXC_DDR_D1		(IOMUXC_BASE_ADDR + 0x02B4)
>+#define IOMUXC_DDR_D0		(IOMUXC_BASE_ADDR + 0x02B8)
>+
>+#define IOMUXC_DDR_DQM1		(IOMUXC_BASE_ADDR + 0x02BC)
>+#define IOMUXC_DDR_DQM0		(IOMUXC_BASE_ADDR + 0x02C0)
>+
>+#define IOMUXC_DDR_DQS1		(IOMUXC_BASE_ADDR + 0x02C4)
>+#define IOMUXC_DDR_DQS0		(IOMUXC_BASE_ADDR + 0x02C8)
>+
>+#define IOMUXC_DDR_RAS		(IOMUXC_BASE_ADDR + 0x02CC)
>+#define IOMUXC_DDR_WE		(IOMUXC_BASE_ADDR + 0x02D0)
>+
>+#define IOMUXC_DDR_ODT0		(IOMUXC_BASE_ADDR + 0x02D4)
>+#define IOMUXC_DDR_ODT1		(IOMUXC_BASE_ADDR + 0x02D8)
>+
>+#define IOMUXC_DDR_DDRBYTE1	(IOMUXC_BASE_ADDR + 0x02DC)
>+#define IOMUXC_DDR_DDRBYTE0	(IOMUXC_BASE_ADDR + 0x02E0)
>+
>+#define IOMUXC_SDHC_DUMMY1	(IOMUXC_BASE_ADDR + 0x02E4)
>+#define IOMUXC_SDHC_DUMMY2	(IOMUXC_BASE_ADDR + 0x02E8)
>+
>+#define IOMUXC_AUD_EXTCLK_INP	(IOMUXC_BASE_ADDR + 0x02EC)
>+#define IOMUXC_ENET_EXTCLK_INP	(IOMUXC_BASE_ADDR + 0x02F0)
>+#define IOMUXC_ENET_TSCLK_INP	(IOMUXC_BASE_ADDR + 0x02F4)
>+
>+struct pad_iomux {
>+	u8 mod;
>+	u8 spd;
>+	u8 sre;
>+	u8 ode;
>+	u8 hys;
>+	u8 dse;
>+	u8 pus;
>+	u8 pke;
>+	u8 pue;
>+	u8 obe;
>+	u8 ibe;
>+};
>+
>+#define PADIOMUX_SET(val, mod, spd, sre, ode, hys,			\
>+		dse, pus, pke, pue, obe, ibe)				\
>+		(val = (((mod & 7) << 20) | ((spd & 3) << 12) |		\
>+		 ((sre & 1) << 11) | ((ode & 1) << 10) |		\
>+		 ((hys & 1) << 9) | ((dse & 7) << 6) |			\
>+		 ((pus & 3) << 4) | ((pke & 1) << 3) |			\
>+		 ((pue & 1) << 2) | ((obe & 1) << 1) |			\
>+		 (ibe & 1)))
>+
>+#define DDRIOMUX_SET(inp, trim, hys, dse, pus, pke, pue)	\
>+		(((inp & 1) << 16) | ((trim & 3) << 14) |	\
>+		 ((hys & 1) << 9) | ((dse & 7) << 6) |		\
>+		 ((pus & 3) << 4) | ((pke & 1) << 3) |		\
>+		 ((pue & 1) << 2))
>+
>+#define MUX_MODE_ALT0		0x00
>+#define MUX_MODE_ALT1		0x01
>+#define MUX_MODE_ALT2		0x02
>+#define MUX_MODE_ALT3		0x03
>+#define MUX_MODE_ALT4		0x04
>+#define MUX_MODE_ALT5		0x05
>+#define MUX_MODE_ALT6		0x06
>+#define MUX_MODE_ALT7		0x07
>+
>+#define MUX_SPD_50MHZ		0x00
>+#define MUX_SPD_100MHZ		0x02
>+#define MUX_SPD_200MHZ		0x03
>+
>+#define MUX_SRE_SLOW		0
>+#define MUX_SRE_FAST		1
>+
>+#define MUX_ODE_CMOS		0
>+#define MUX_ODE_OPEN		1
>+
>+#define MUX_HYS_CMOS		0
>+#define MUX_HYS_SCHMITT		1
>+
>+#define MUX_DSE_20_OHM		7
>+#define MUX_DSE_25_OHM		6
>+#define MUX_DSE_30_OHM		5
>+#define MUX_DSE_37_OHM		4
>+#define MUX_DSE_50_OHM		3
>+#define MUX_DSE_75_OHM		2
>+#define MUX_DSE_150_OHM		1
>+#define MUX_DSE_DIS		0
>+
>+#define MUX_PUS_22KOHM_UP	3
>+#define MUX_PUS_100KOHM_UP	2
>+#define MUX_PUS_47KOHM_UP	1
>+#define MUX_PUS_100KOHM_DN	0
>+
>+#define MUX_PKE_EN		1
>+#define MUX_PKE_DIS		0
>+
>+#define MUX_PUE_PULLEN		1
>+#define MUX_PUE_KEEPEREN	0
>+
>+#define MUX_OBE_EN		1
>+#define MUX_OBE_DIS		0
>+
>+#define MUX_IBE_EN		1
>+#define MUX_IBE_DIS		0
>+
>+#define MUX_DDR_INPUT_DIFF	1
>+#define MUX_DDR_INPUT_CMOS	0
>+
>+#define MUX_DDR_TRIM_150PS	3
>+#define MUX_DDR_TRIM_100PS	2
>+#define MUX_DDR_TRIM_50PS	1
>+#define MUX_DDR_TRIM_MIN	0
>+
>+void pad_iomux_set(u32 pad_addr, struct pad_iomux *padio);
>+
>+#endif				/*  __MACH_VYBRID_IOMUX_H__ */
>diff --git a/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
>b/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
>new file mode 100644
>index 0000000..9575f73
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
>@@ -0,0 +1,213 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#ifndef __SERIAL_VYBRID_H__
>+#define __SERIAL_VYBRID_H__
>+
>+#define UBDH		0x00
>+#define UBDL		0x01
>+#define UC1		0x02
>+#define UC2		0x03
>+#define US1		0x04
>+#define US2		0x05
>+#define UC3		0x06
>+#define UD		0x07
>+#define UMA1		0x08
>+#define UMA2		0x09
>+#define UC4		0x0A
>+#define UC5		0x0B
>+#define UED		0x0C
>+#define UMODEM		0x0D
>+#define UIR		0x0E
>+#define UPFIFO		0x10
>+#define UCFIFO		0x11
>+#define USFIFO		0x12
>+#define UTWFIFO		0x13
>+#define UTCFIFO		0x14
>+#define URWFIFO		0x15
>+#define URCFIFO		0x16
>+#define UC7816		0x18
>+#define UIE7816		0x19
>+#define UIS7816		0x1A
>+#define UWP7816T0	0x1B
>+#define UWP7816T1	0x1B
>+#define UWN7816		0x1C
>+#define UWF7816		0x1D
>+#define UET78416	0x1E
>+#define UTL7816		0x1F
>+#define UC6		0x21
>+#define UPCTH		0x22
>+#define UPCTL		0x23
>+#define UB1T		0x24
>+#define USDTH		0x25
>+#define USDTL		0x26
>+#define UPRE		0x27
>+#define UTPL		0x28
>+#define UIE		0x29
>+#define UWB		0x2A
>+#define US3		0x2B
>+#define US4		0x2C
>+#define UPRL		0x2D
>+#define URPREL		0x2E
>+#define UCPW		0x2F
>+#define URIDT		0x30
>+#define UTIDT		0x31
>+
>+#define UBDH_LBKDIE	(1 << 7)
>+#define UBDH_RXEDGIE	(1 << 6)
>+#define UBDH_SBR(x)	(x & 0x1F)
>+
>+#define UC1_LOOPS	(1 << 7)
>+#define UC1_SWAI	(1 << 6)
>+#define UC1_RSRC	(1 << 5)
>+#define UC1_M		(1 << 4)
>+#define UC1_WAKE	(1 << 3)
>+#define UC1_ILT		(1 << 2)
>+#define UC1_PE		(1 << 1)
>+#define UC1_PT		(1 << 0)
>+
>+#define UC2_TIE		(1 << 7)
>+#define UC2_TCIE	(1 << 6)
>+#define UC2_RIE		(1 << 5)
>+#define UC2_ILIE	(1 << 4)
>+#define UC2_TE		(1 << 3)
>+#define UC2_RE		(1 << 2)
>+#define UC2_RWU		(1 << 1)
>+#define UC2_SBK		(1 << 0)
>+
>+#define US1_TDRE	(1 << 7)
>+#define US1_TC		(1 << 6)
>+#define US1_RDRF	(1 << 5)
>+#define US1_IDLE	(1 << 4)
>+#define US1_OR		(1 << 3)
>+#define US1_NF		(1 << 2)
>+#define US1_FE		(1 << 1)
>+#define US1_PF		(1 << 0)
>+
>+#define US2_LBKDIF	(1 << 7)
>+#define US2_RXEDGIF	(1 << 6)
>+#define US2_MSBF	(1 << 5)
>+#define US2_RXINV	(1 << 4)
>+#define US2_RWUID	(1 << 3)
>+#define US2_BRK13	(1 << 2)
>+#define US2_RBKDE	(1 << 1)
>+#define US2_RAF		(1 << 0)
>+
>+#define UC3_R8		(1 << 7)
>+#define UC3_T8		(1 << 6)
>+#define UC3_TXDIR	(1 << 5)
>+#define UC3_TXINV	(1 << 4)
>+#define UC3_ORIE	(1 << 3)
>+#define UC3_NEIF	(1 << 2)
>+#define UC3_FEIF	(1 << 1)
>+#define UC3_PEIE	(1 << 0)
>+
>+#define UC4_MAEN1	(1 << 7)
>+#define UC4_MAEN2	(1 << 6)
>+#define UC4_M10		(1 << 5)
>+#define UC4_BRFA(x)	(x & 0x1F)
>+
>+#define UC5_TDMAS	(1 << 7)
>+#define UC5_RDMAS	(1 << 5)
>+
>+#define UED_NOISY	(1 << 7)
>+#define UED_PARITYE	(1 << 6)
>+
>+#define UMODEM_RXRTSE	(1 << 3)
>+#define UMODEM_TXRTSPOL	(1 << 2)
>+#define UMODEM_TXRTSE	(1 << 1)
>+#define UMODEM_TXCTSE	(1 << 0)
>+
>+#define UIR_IREN	(1 << 2)
>+#define UIR_TNP(x)	(x & 3)
>+
>+#define UPFIFO_TXFE	(1 << 7)
>+#define UPFIFO_TXFSZ(x)	((x & 7) << 4)
>+#define UPFIFO_RXFE	(1 << 3)
>+#define UPFIFO_RXFSZ(x)	((x & 7) << 0)
>+
>+#define UCFIFO_TXFLUSH	(1 << 7)
>+#define UCFIFO_RXFLUSH	(1 << 6)
>+#define UCFIFO_TXOFE	(1 << 1)
>+#define UCFIFO_RXUFE	(1 << 0)
>+
>+#define USFIFO_TXEMPT	(1 << 7)
>+#define USFIFO_RXEMPT	(1 << 6)
>+#define USFIFO_TXOF	(1 << 1)
>+#define USFIFO_RXUF	(1 << 0)
>+
>+#define UC7816_ONACK	(1 << 4)
>+#define UC7816_ANACK	(1 << 3)
>+#define UC7816_INIT	(1 << 2)
>+#define UC7816_TTYPE	(1 << 1)
>+#define UC7816_7816E	(1 << 0)
>+
>+#define UIE7816_WTE	(1 << 7)
>+#define UIE7816_CWTE	(1 << 6)
>+#define UIE7816_BWTE	(1 << 5)
>+#define UIE7816_INITDE	(1 << 4)
>+#define UIE7816_GTVE	(1 << 2)
>+#define UIE7816_TXTE	(1 << 1)
>+#define UIE7816_RXTE	(1 << 0)
>+
>+#define UIS7816_WTE	(1 << 7)
>+#define UIS7816_CWTE	(1 << 6)
>+#define UIS7816_BWTE	(1 << 5)
>+#define UIS7816_INITDE	(1 << 4)
>+#define UIS7816_GTVE	(1 << 2)
>+#define UIS7816_TXTE	(1 << 1)
>+#define UIS7816_RXTE	(1 << 0)
>+
>+#define UWP7816T1_CWI(x)	((x & 0xf) << 4)
>+#define UWP7816T1_BWI(x)	((x & 0xf) << 0)
>+
>+#define UET78416_TXTHRESHOLD(x)	((x & 0xf) << 4)
>+#define UET78416_RXTHRESHOLD(x)	((x & 0xf) << 0)
>+
>+#define UC6_EN709	(1 << 7)
>+#define UC6_TX709	(1 << 6)
>+#define UC6_CE		(1 << 5)
>+#define UC6_CP		(1 << 4)
>+
>+#define UIE_WBEIE	(1 << 6)
>+#define UIE_ISDIE	(1 << 5)
>+#define UIE_PRXIE	(1 << 4)
>+#define UIE_PTXIE	(1 << 3)
>+#define UIE_PCTEIE	(1 << 2)
>+#define UIE_PSIE	(1 << 1)
>+#define UIE_TXFIE	(1 << 0)
>+
>+#define US3_PEF		(1 << 7)
>+#define US3_WBEF	(1 << 6)
>+#define US3_ISD		(1 << 5)
>+#define US3_PRXF	(1 << 4)
>+#define US3_PTXF	(1 << 3)
>+#define US3_PCTEF	(1 << 2)
>+#define US3_PSF		(1 << 1)
>+#define US3_TXFF	(1 << 0)
>+
>+#define US4_INITF	(1 << 4)
>+#define US4_CDET(x)	((x & 3) << 2)
>+#define US4_ILCV	(1 << 1)
>+#define US4_FE		(1 << 0)
>+
>+#endif			/* __SERIAL_VYBRID_H__ */
>diff --git a/arch/arm/include/asm/arch-vybrid/sys_proto.h
>b/arch/arm/include/asm/arch-vybrid/sys_proto.h
>new file mode 100644
>index 0000000..7e2de97
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-vybrid/sys_proto.h
>@@ -0,0 +1,30 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#ifndef _SYS_PROTO_H_
>+#define _SYS_PROTO_H_
>+
>+u32 get_cpu_rev(void);
>+#define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
>+void sdelay(unsigned long);
>+
>+#endif
>diff --git a/arch/arm/include/asm/arch-vybrid/timer.h
>b/arch/arm/include/asm/arch-vybrid/timer.h
>new file mode 100644
>index 0000000..55497e3
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-vybrid/timer.h
>@@ -0,0 +1,405 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#ifndef __ASM_ARCH_TIMER_H
>+#define __ASM_ARCH_TIMER_H
>+
>+struct ftm_regs {
>+	u32 sc;		/* 0x00 */
>+	u32 cnt;	/* 0x04 */
>+	u32 mod;	/* 0x08 */
>+	u32 c0sc;	/* 0x0C */
>+	u32 c0v;	/* 0x10 */
>+	u32 c1sc;	/* 0x14 */
>+	u32 c1v;	/* 0x18 */
>+	u32 c2sc;	/* 0x1C */
>+	u32 c2v;	/* 0x20 */
>+	u32 c3sc;	/* 0x24 */
>+	u32 c3v;	/* 0x28 */
>+	u32 c4sc;	/* 0x2C */
>+	u32 c4v;	/* 0x30 */
>+	u32 c5sc;	/* 0x34 */
>+	u32 c5v;	/* 0x38 */
>+	u32 c6sc;	/* 0x3C */
>+	u32 c6v;	/* 0x40 */
>+	u32 c7sc;	/* 0x44 */
>+	u32 c7v;	/* 0x48 */
>+	u32 cntin;	/* 0x4C */
>+	u32 status;	/* 0x50 */
>+	u32 mode;	/* 0x54 */
>+	u32 sync;	/* 0x58 */
>+	u32 outinit;	/* 0x5C */
>+	u32 outmask;	/* 0x60 */
>+	u32 combine;	/* 0x64 */
>+	u32 deadtime;	/* 0x68 */
>+	u32 exttrig;	/* 0x6C */
>+	u32 pol;	/* 0x70 */
>+	u32 fms;	/* 0x74 */
>+	u32 filter;	/* 0x78 */
>+	u32 fltctrl;	/* 0x7C */
>+	u32 qdctrl;	/* 0x80 */
>+	u32 conf;	/* 0x84 */
>+	u32 fltpol;	/* 0x88 */
>+	u32 synconf;	/* 0x8C */
>+	u32 invctrl;	/* 0x90 */
>+	u32 swoctrl;	/* 0x94 */
>+	u32 pwmload;	/* 0x98 */
>+};
>+
>+struct pit2_regs {
>+	u32 ldval;	/* 0x00 */
>+	u32 cval;	/* 0x04 */
>+	u32 tctrl;	/* 0x08 */
>+	u32 tflg;	/* 0x0C */
>+};
>+
>+struct pit_regs {
>+	u32 mcr;	/* 0x00 */
>+	u32 rsvd0[55];
>+	u32 ltmr64h;	/* 0xE0 */
>+	u32 ltmr64l;	/* 0xE4 */
>+	u32 rsvd1[6];
>+	struct pit2_regs counter[8];	/* 0x100 */
>+};
>+
>+struct lptmr_regs {
>+	u32 csr;	/* 0x00 */
>+	u32 psr;	/* 0x04 */
>+	u32 cmr;	/* 0x08 */
>+	u32 cnr;	/* 0x0C */
>+};
>+
>+/* Flex Timer */
>+#define FTM_SC			(FTM_BASE_ADDR + 0x00)
>+#define FTM_CNT			(FTM_BASE_ADDR + 0x04)
>+#define FTM_MOD			(FTM_BASE_ADDR + 0x08)
>+#define FTM_C0SC		(FTM_BASE_ADDR + 0x0C)
>+#define FTM_C0V			(FTM_BASE_ADDR + 0x10)
>+#define FTM_C1SC		(FTM_BASE_ADDR + 0x14)
>+#define FTM_C1V			(FTM_BASE_ADDR + 0x18)
>+#define FTM_C2SC		(FTM_BASE_ADDR + 0x1C)
>+#define FTM_C2V			(FTM_BASE_ADDR + 0x20)
>+#define FTM_C3SC		(FTM_BASE_ADDR + 0x24)
>+#define FTM_C3V			(FTM_BASE_ADDR + 0x28)
>+#define FTM_C4SC		(FTM_BASE_ADDR + 0x2C)
>+#define FTM_C4V			(FTM_BASE_ADDR + 0x30)
>+#define FTM_C5SC		(FTM_BASE_ADDR + 0x34)
>+#define FTM_C5V			(FTM_BASE_ADDR + 0x38)
>+#define FTM_C6SC		(FTM_BASE_ADDR + 0x3C)
>+#define FTM_C6V			(FTM_BASE_ADDR + 0x40)
>+#define FTM_C7SC		(FTM_BASE_ADDR + 0x44)
>+#define FTM_C7V			(FTM_BASE_ADDR + 0x48)
>+#define FTM_CNTIN		(FTM_BASE_ADDR + 0x4C)
>+#define FTM_STATUS		(FTM_BASE_ADDR + 0x50)
>+#define FTM_MODE		(FTM_BASE_ADDR + 0x54)
>+#define FTM_SYNC		(FTM_BASE_ADDR + 0x58)
>+#define FTM_OUTINIT		(FTM_BASE_ADDR + 0x5C)
>+#define FTM_OUTMASK		(FTM_BASE_ADDR + 0x60)
>+#define FTM_COMBINE		(FTM_BASE_ADDR + 0x64)
>+#define FTM_DEADTIME		(FTM_BASE_ADDR + 0x68)
>+#define FTM_EXTTRIG		(FTM_BASE_ADDR + 0x6C)
>+#define FTM_POL			(FTM_BASE_ADDR + 0x70)
>+#define FTM_FMS			(FTM_BASE_ADDR + 0x74)
>+#define FTM_FILTER		(FTM_BASE_ADDR + 0x78)
>+#define FTM_FLTCTRL		(FTM_BASE_ADDR + 0x7C)
>+#define FTM_QDCTRL		(FTM_BASE_ADDR + 0x80)
>+#define FTM_CONF		(FTM_BASE_ADDR + 0x84)
>+#define FTM_FLTPOL		(FTM_BASE_ADDR + 0x88)
>+#define FTM_SYNCONF		(FTM_BASE_ADDR + 0x8C)
>+#define FTM_INVCTRL		(FTM_BASE_ADDR + 0x90)
>+#define FTM_SWOCTRL		(FTM_BASE_ADDR + 0x94)
>+#define FTM_PWMLOAD		(FTM_BASE_ADDR + 0x98)

You are already provide the c structure for the FTM, do you still need the
Base + offset define here?

>+
>+#define FTM_SC_TOF		(1 << 7)
>+#define FTM_SC_TOIE		(1 << 6)
>+#define FTM_SC_CPWMS		(1 << 5)
>+#define FTM_SC_CLKS(x)		((x & 3) << 3)
>+#define FTM_SC_PS(x)		((x & 7) << 0)
>+
>+#define FTM_CNT_COUNT(x)	(x & 0xFFFF)
>+
>+#define FTM_MOD_MOD(x)		(x & 0xFFFF)
>+
>+#define FTM_CnSC_CHF		(1 << 7)
>+#define FTM_CnSC_CHIE		(1 << 6)
>+#define FTM_CnSC_MSB		(1 << 5)
>+#define FTM_CnSC_MSA		(1 << 4)
>+#define FTM_CnSC_ELSB		(1 << 3)
>+#define FTM_CnSC_ELSA		(1 << 2)
>+#define FTM_CnSC_DMA		(1 << 0)
>+
>+#define FTM_CnV_VAL(x)		(x & 0xFFFF)
>+
>+#define FTM_CNTIN_INIT(x)	(x & 0xFFFF)
>+
>+#define FTM_STATUS_CH7F		(1 << 7)
>+#define FTM_STATUS_CH6F		(1 << 6)
>+#define FTM_STATUS_CH5F		(1 << 5)
>+#define FTM_STATUS_CH4F		(1 << 4)
>+#define FTM_STATUS_CH3F		(1 << 3)
>+#define FTM_STATUS_CH2F		(1 << 2)
>+#define FTM_STATUS_CH1F		(1 << 1)
>+#define FTM_STATUS_CH0F		(1 << 0)
>+
>+#define FTM_MODE_FAULTIE	(1 << 7)
>+#define FTM_MODE_FAULTM(x)	((x & 3) << 5)
>+#define FTM_MODE_CAPTEST	(1 << 4)
>+#define FTM_MODE_PWMSYNC	(1 << 3)
>+#define FTM_MODE_WPDIS		(1 << 2)
>+#define FTM_MODE_INIT		(1 << 1)
>+#define FTM_MODE_FTMEN		(1 << 0)
>+
>+#define FTM_SYNC_SWSYNC		(1 << 7)
>+#define FTM_SYNC_TRIG2		(1 << 6)
>+#define FTM_SYNC_TRIG1		(1 << 5)
>+#define FTM_SYNC_TRIG0		(1 << 4)
>+#define FTM_SYNC_SYNCHOM	(1 << 3)
>+#define FTM_SYNC_REINIT		(1 << 2)
>+#define FTM_SYNC_CNTMAX		(1 << 1)
>+#define FTM_SYNC_CNTMIN		(1 << 0)
>+
>+#define FTM_OUTINIT_CH7OI	(1 << 7)
>+#define FTM_OUTINIT_CH6OI	(1 << 6)
>+#define FTM_OUTINIT_CH5OI	(1 << 5)
>+#define FTM_OUTINIT_CH4OI	(1 << 4)
>+#define FTM_OUTINIT_CH3OI	(1 << 3)
>+#define FTM_OUTINIT_CH2OI	(1 << 2)
>+#define FTM_OUTINIT_CH1OI	(1 << 1)
>+#define FTM_OUTINIT_CH0OI	(1 << 0)
>+
>+#define FTM_OUTMASK_CH7OM	(1 << 7)
>+#define FTM_OUTMASK_CH6OM	(1 << 6)
>+#define FTM_OUTMASK_CH5OM	(1 << 5)
>+#define FTM_OUTMASK_CH4OM	(1 << 4)
>+#define FTM_OUTMASK_CH3OM	(1 << 3)
>+#define FTM_OUTMASK_CH2OM	(1 << 2)
>+#define FTM_OUTMASK_CH1OM	(1 << 1)
>+#define FTM_OUTMASK_CH0OM	(1 << 0)
>+
>+#define FTM_COMBINE_FAULTEN3	(1 << 30)
>+#define FTM_COMBINE_SYNCEN3	(1 << 29)
>+#define FTM_COMBINE_DTEN3	(1 << 28)
>+#define FTM_COMBINE_DECAP3	(1 << 27)
>+#define FTM_COMBINE_DECAPEN3	(1 << 26)
>+#define FTM_COMBINE_COMP3	(1 << 25)
>+#define FTM_COMBINE_COMBINE3	(1 << 24)
>+#define FTM_COMBINE_FAULTEN2	(1 << 22)
>+#define FTM_COMBINE_SYNCEN2	(1 << 21)
>+#define FTM_COMBINE_DTEN2	(1 << 20)
>+#define FTM_COMBINE_DECAP2	(1 << 19)
>+#define FTM_COMBINE_DECAPEN2	(1 << 18)
>+#define FTM_COMBINE_COMP2	(1 << 17)
>+#define FTM_COMBINE_COMBINE2	(1 << 16)
>+#define FTM_COMBINE_FAULTEN1	(1 << 14)
>+#define FTM_COMBINE_SYNCEN1	(1 << 13)
>+#define FTM_COMBINE_DTEN1	(1 << 12)
>+#define FTM_COMBINE_DECAP1	(1 << 11)
>+#define FTM_COMBINE_DECAPEN1	(1 << 10)
>+#define FTM_COMBINE_COMP1	(1 << 9)
>+#define FTM_COMBINE_COMBINE1	(1 << 8)
>+#define FTM_COMBINE_FAULTEN0	(1 << 6)
>+#define FTM_COMBINE_SYNCEN0	(1 << 5)
>+#define FTM_COMBINE_DTEN0	(1 << 4)
>+#define FTM_COMBINE_DECAP0	(1 << 3)
>+#define FTM_COMBINE_DECAPEN0	(1 << 2)
>+#define FTM_COMBINE_COMP0	(1 << 1)
>+#define FTM_COMBINE_COMBINE0	(1 << 0)
>+
>+#define FTM_DEADTIME_DTPS(x)	((x & 3) << 6)
>+#define FTM_DEADTIME_DTVAL(x)	((x & 0x3F) << 0)
>+
>+#define FTM_EXTTRIG_TRIGF	(1 << 7)
>+#define FTM_EXTTRIG_INITTRIGEN	(1 << 6)
>+#define FTM_EXTTRIG_CH1TRIG	(1 << 5)
>+#define FTM_EXTTRIG_CH0TRIG	(1 << 4)
>+#define FTM_EXTTRIG_CH5TRIG	(1 << 3)
>+#define FTM_EXTTRIG_CH4TRIG	(1 << 2)
>+#define FTM_EXTTRIG_CH3TRIG	(1 << 1)
>+#define FTM_EXTTRIG_CH2TRIG	(1 << 0)
>+
>+#define FTM_POL_POL7		(1 << 7)
>+#define FTM_POL_POL6		(1 << 6)
>+#define FTM_POL_POL5		(1 << 5)
>+#define FTM_POL_POL4		(1 << 4)
>+#define FTM_POL_POL3		(1 << 3)
>+#define FTM_POL_POL2		(1 << 2)
>+#define FTM_POL_POL1		(1 << 1)
>+#define FTM_POL_POL0		(1 << 0)
>+
>+#define FTM_FMS_FAULTF		(1 << 7)
>+#define FTM_FMS_WPEN		(1 << 6)
>+#define FTM_FMS_FAULTIN		(1 << 5)
>+#define FTM_FMS_FAULTF3		(1 << 3)
>+#define FTM_FMS_FAULTF2		(1 << 2)
>+#define FTM_FMS_FAULTF1		(1 << 1)
>+#define FTM_FMS_FAULTF0		(1 << 0)
>+
>+#define FTM_FILTER_CH3FVAL(x)	((x & 0xF) << 12)
>+#define FTM_FILTER_CH2FVAL(x)	((x & 0xF) << 8)
>+#define FTM_FILTER_CH1FVAL(x)	((x & 0xF) << 4)
>+#define FTM_FILTER_CH0FVAL(x)	((x & 0xF) << 0)
>+
>+#define FTM_FLTCTRL_FFVAL(x)	((x & 0xF) << 8)
>+#define FTM_FLTCTRL_FFLTR3EN	(1 << 7)
>+#define FTM_FLTCTRL_FFLTR2EN	(1 << 6)
>+#define FTM_FLTCTRL_FFLTR1EN	(1 << 5)
>+#define FTM_FLTCTRL_FFLTR0EN	(1 << 4)
>+#define FTM_FLTCTRL_FAULT3EN	(1 << 3)
>+#define FTM_FLTCTRL_FAULT2EN	(1 << 2)
>+#define FTM_FLTCTRL_FAULT1EN	(1 << 1)
>+#define FTM_FLTCTRL_FAULT0EN	(1 << 0)
>+
>+#define FTM_QDCTRL_PHAFLTREN	(1 << 7)
>+#define FTM_QDCTRL_PHBFLTREN	(1 << 6)
>+#define FTM_QDCTRL_PHAPOL	(1 << 5)
>+#define FTM_QDCTRL_PHBPOL	(1 << 4)
>+#define FTM_QDCTRL_QUADMODE	(1 << 3)
>+#define FTM_QDCTRL_QUADIR	(1 << 2)
>+#define FTM_QDCTRL_TOFDIR	(1 << 1)
>+#define FTM_QDCTRL_QUADEN	(1 << 0)
>+
>+#define FTM_CONF_GTBEOUT	(1 << 10)
>+#define FTM_CONF_GTBEEN		(1 << 9)
>+#define FTM_CONF_BDMMODE(x)	((x & 3) << 6)
>+#define FTM_CONF_NUMTOF(x)	((x & 0x1F) << 0)
>+
>+#define FTM_FLTPOL_FLT3POL	(1 << 3)
>+#define FTM_FLTPOL_FLT2POL	(1 << 2)
>+#define FTM_FLTPOL_FLT1POL	(1 << 1)
>+#define FTM_FLTPOL_FLT0POL	(1 << 0)
>+
>+#define FTM_SYNCONF_HWSOC	(1 << 20)
>+#define FTM_SYNCONF_HWINVC	(1 << 19)
>+#define FTM_SYNCONF_HWOM	(1 << 18)
>+#define FTM_SYNCONF_HWWRBUF	(1 << 17)
>+#define FTM_SYNCONF_HWRSTCNT	(1 << 16)
>+#define FTM_SYNCONF_SWSOC	(1 << 12)
>+#define FTM_SYNCONF_SWINVC	(1 << 11)
>+#define FTM_SYNCONF_SWOM	(1 << 10)
>+#define FTM_SYNCONF_SWWRBUF	(1 << 9)
>+#define FTM_SYNCONF_SWRSTCNT	(1 << 8)
>+#define FTM_SYNCONF_SYNCMODE	(1 << 7)
>+#define FTM_SYNCONF_SWOC	(1 << 5)
>+#define FTM_SYNCONF_INVC	(1 << 4)
>+#define FTM_SYNCONF_CNTINC	(1 << 2)
>+#define FTM_SYNCONF_HWTRIGMODE	(1 << 0)
>+
>+#define FTM_INVCTRL_INV3EN	(1 << 3)
>+#define FTM_INVCTRL_INV2EN	(1 << 2)
>+#define FTM_INVCTRL_INV1EN	(1 << 1)
>+#define FTM_INVCTRL_INV0EN	(1 << 0)
>+
>+#define FTM_SWOCTRL_CH7OCV	(1 << 15)
>+#define FTM_SWOCTRL_CH6OCV	(1 << 14)
>+#define FTM_SWOCTRL_CH5OCV	(1 << 13)
>+#define FTM_SWOCTRL_CH4OCV	(1 << 12)
>+#define FTM_SWOCTRL_CH3OCV	(1 << 11)
>+#define FTM_SWOCTRL_CH2OCV	(1 << 10)
>+#define FTM_SWOCTRL_CH1OCV	(1 << 9)
>+#define FTM_SWOCTRL_CH0OCV	(1 << 8)
>+#define FTM_SWOCTRL_CH7OC	(1 << 7)
>+#define FTM_SWOCTRL_CH6OC	(1 << 6)
>+#define FTM_SWOCTRL_CH5OC	(1 << 5)
>+#define FTM_SWOCTRL_CH4OC	(1 << 4)
>+#define FTM_SWOCTRL_CH3OC	(1 << 3)
>+#define FTM_SWOCTRL_CH2OC	(1 << 2)
>+#define FTM_SWOCTRL_CH1OC	(1 << 1)
>+#define FTM_SWOCTRL_CH0OC	(1 << 0)
>+
>+#define FTM_PWMLOAD_LDOK	(1 << 9)
>+#define FTM_PWMLOAD_CH7SEL	(1 << 7)
>+#define FTM_PWMLOAD_CH6SEL	(1 << 6)
>+#define FTM_PWMLOAD_CH5SEL	(1 << 5)
>+#define FTM_PWMLOAD_CH4SEL	(1 << 4)
>+#define FTM_PWMLOAD_CH3SEL	(1 << 3)
>+#define FTM_PWMLOAD_CH2SEL	(1 << 2)
>+#define FTM_PWMLOAD_CH1SEL	(1 << 1)
>+#define FTM_PWMLOAD_CH0SEL	(1 << 0)
>+
>+/* Periodic Interrupt Timer */
>+#define PIT_MCR			(PIT_BASE_ADDR + 0x00)
>+#define PIT_LTMR64H		(PIT_BASE_ADDR + 0xE0)
>+#define PIT_LTMR64L		(PIT_BASE_ADDR + 0xE4)
>+#define PIT_LDVAL0		(PIT_BASE_ADDR + 0x100)
>+#define PIT_CVAL0		(PIT_BASE_ADDR + 0x104)
>+#define PIT_TCTRL0		(PIT_BASE_ADDR + 0x108)
>+#define PIT_TFLG0		(PIT_BASE_ADDR + 0x10C)
>+#define PIT_LDVAL1		(PIT_BASE_ADDR + 0x110)
>+#define PIT_CVAL1		(PIT_BASE_ADDR + 0x114)
>+#define PIT_TCTRL1		(PIT_BASE_ADDR + 0x118)
>+#define PIT_TFLG1		(PIT_BASE_ADDR + 0x11C)
>+#define PIT_LDVAL2		(PIT_BASE_ADDR + 0x120)
>+#define PIT_CVAL2		(PIT_BASE_ADDR + 0x124)
>+#define PIT_TCTRL2		(PIT_BASE_ADDR + 0x128)
>+#define PIT_TFLG2		(PIT_BASE_ADDR + 0x12C)
>+#define PIT_LDVAL3		(PIT_BASE_ADDR + 0x130)
>+#define PIT_CVAL3		(PIT_BASE_ADDR + 0x134)
>+#define PIT_TCTRL3		(PIT_BASE_ADDR + 0x138)
>+#define PIT_TFLG3		(PIT_BASE_ADDR + 0x13C)
>+#define PIT_LDVAL4		(PIT_BASE_ADDR + 0x140)
>+#define PIT_CVAL4		(PIT_BASE_ADDR + 0x144)
>+#define PIT_TCTRL4		(PIT_BASE_ADDR + 0x148)
>+#define PIT_TFLG4		(PIT_BASE_ADDR + 0x14C)
>+#define PIT_LDVAL5		(PIT_BASE_ADDR + 0x150)
>+#define PIT_CVAL5		(PIT_BASE_ADDR + 0x154)
>+#define PIT_TCTRL5		(PIT_BASE_ADDR + 0x158)
>+#define PIT_TFLG5		(PIT_BASE_ADDR + 0x15C)
>+#define PIT_LDVAL6		(PIT_BASE_ADDR + 0x160)
>+#define PIT_CVAL6		(PIT_BASE_ADDR + 0x164)
>+#define PIT_TCTRL6		(PIT_BASE_ADDR + 0x168)
>+#define PIT_TFLG6		(PIT_BASE_ADDR + 0x16C)
>+#define PIT_LDVAL7		(PIT_BASE_ADDR + 0x170)
>+#define PIT_CVAL7		(PIT_BASE_ADDR + 0x174)
>+#define PIT_TCTRL7		(PIT_BASE_ADDR + 0x178)
>+#define PIT_TFLG7		(PIT_BASE_ADDR + 0x17C)

Ditto,

>+
>+#define PIT_MCR_MDIS		(1 << 1)
>+#define PIT_MCR_FRZ		(1 << 0)
>+
>+#define PIT_TCTRL_CHN		(1 << 2)
>+#define PIT_TCTRL_TIE		(1 << 1)
>+#define PIT_TCTRL_TEN		(1 << 0)
>+
>+#define PIT_TFLG_TIF		(1 << 0)
>+
>+/* Low Power Timer */
>+#define LPTMR_CSR		(LPTMR_BASE_ADDR + 0x00)
>+#define LPTMR_PSR		(LPTMR_BASE_ADDR + 0x04)
>+#define LPTMR_CMR		(LPTMR_BASE_ADDR + 0x08)
>+#define LPTMR_CNR		(LPTMR_BASE_ADDR + 0x0C)
>+
>+#define LPTMR_CSR_TCF		(1 << 7)
>+#define LPTMR_CSR_TIE		(1 << 6)
>+#define LPTMR_CSR_TPS(x)	((x & 3) << 4)
>+#define LPTMR_CSR_TPP		(1 << 3)
>+#define LPTMR_CSR_TFC		(1 << 2)
>+#define LPTMR_CSR_TMS		(1 << 1)
>+#define LPTMR_CSR_TEN		(1 << 0)
>+
>+#define LPTMR_PSR_PRESCALE(x)	((x & 0x0F) << 3)
>+#define LPTMR_PSR_PBYP		(1 << 2)
>+#define LPTMR_PSR_PCS(x)	((x & 0x03) << 0)
>+
>+#define LPTMR_CMR_COMPARE(x)	(x & 0xFFFF)
>+#define LPTMR_CNR_COUNTER(x)	(x & 0xFFFF)
>+
>+#endif /* __ASM_ARCH_TIMER_H */
>diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
>b/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
>new file mode 100644
>index 0000000..225a1e1
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
>@@ -0,0 +1,88 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#ifndef __ASM_ARCH_VYBRID_PINS_H__
>+#define __ASM_ARCH_VYBRID_PINS_H__
>+
>+#ifndef __ASSEMBLY__
>+
>+/*!
>+ * Starting bit position within each entry of \b iomux_pins to
>represent the
>+ * MUX control register offset
>+ */
>+#define MUX_I			0
>+/*!
>+ * Starting bit position within each entry of \b iomux_pins to
>represent the
>+ * PAD control register offset
>+ */
>+#define PAD_I			10
>+/*!
>+ * Starting bit position within each entry of \b iomux_pins to
>represent which
>+ * mux mode is for GPIO (0-based)
>+ */
>+#define GPIO_I			21
>+
>+#define MUX_IO_P                29
>+#define MUX_IO_I                24
>+#define IOMUX_TO_GPIO(pin)      ((((unsigned int)pin >> MUX_IO_P) * \
>+					GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
>+					((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
>+#define IOMUX_TO_IRQ(pin)       (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
>+#define GPIO_TO_PORT(n)         (n / GPIO_NUM_PIN)
>+#define GPIO_TO_INDEX(n)        (n % GPIO_NUM_PIN)
>+
>+#define NON_GPIO_PORT		0x7
>+#define PIN_TO_MUX_MASK		((1 << (PAD_I - MUX_I)) - 1)
>+#define PIN_TO_PAD_MASK		((1 << (GPIO_I - PAD_I)) - 1)
>+#define PIN_TO_ALT_GPIO_MASK		((1 << (MUX_IO_I - GPIO_I)) - 1)
>+
>+#define NON_MUX_I              PIN_TO_MUX_MASK
>+#define NON_PAD_I              PIN_TO_PAD_MASK
>+
>+#define MUX_I_START		0x001C
>+#define PAD_I_START		0x3F0
>+#define INPUT_CTL_START		0x8C4
>+#define MUX_I_END		(PAD_I_START - 4)
>+
>+#define _VYBRID_BUILD_PIN(gp, gi, ga, mi, pi) \
>+	(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
>+	((mi) << MUX_I) | \
>+	((pi - PAD_I_START) << PAD_I) | \
>+	((ga) << GPIO_I))
>+
>+#define _VYBRID_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
>+	_VYBRID_BUILD_PIN(gp, gi, ga, mi, pi)
>+
>+#define _VYBRID_BUILD_NON_GPIO_PIN(mi, pi) \
>+	_VYBRID_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
>+
>+#define PIN_TO_IOMUX_MUX(pin)	((pin >> MUX_I) & PIN_TO_MUX_MASK)
>+#define PIN_TO_IOMUX_PAD(pin)	((pin >> PAD_I) & PIN_TO_PAD_MASK)
>+#define PIN_TO_ALT_GPIO(pin)	((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
>+#define PIN_TO_IOMUX_INDEX(pin)	(PIN_TO_IOMUX_MUX(pin) >> 2)
>+
>+enum iomux_input_select {
>+	AUDMUX_P4_INPUT = 0,
>+};

Could you please consider the common iomux-v3 code?

Jason Liu
>+
>+#endif				/* __ASSEMBLY__ */
>+#endif				/* __ASM_ARCH_VYBRID_PINS_H__ */
>diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-regs.h
>b/arch/arm/include/asm/arch-vybrid/vybrid-regs.h
>new file mode 100644
>index 0000000..51cfba5

[..]



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