[U-Boot] [PATCH v4 01/10] imx: Homogenize and fix fuse register definitions
Stefano Babic
sbabic at denx.de
Thu Apr 25 09:24:24 CEST 2013
On 23/04/2013 22:17, Benoît Thébaudeau wrote:
> IIM:
> - Homogenize prg_p naming (the reference manuals are not always self-consistent
> for that).
> - Add missing SCSx and bank registers.
> - Fix the number of banks on i.MX53.
>
> OCOTP:
> - Rename iim to ocotp in order to avoid confusion.
> - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the
> reference manual.
> - Merge the existing spinoff gp1 fuse definition on i.MX6.
> - Fix the number of banks on i.MX6.
>
> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau at advansee.com>
> ---
Very nice work, Benoît !
Acked-by: Stefano Babic <sbabic at denx.de>
Best regards,
Stefano Babic
> Changes in v4:
> - Convert spaces to tabs.
>
> Changes in v3:
> - Rebase against latest u-boot-imx/master.
> - Fix the number of banks on i.MX6.
> - Rename iim to ocotp on i.MX6 in order to avoid confusion, and merge in the
> existing gp1 fuse definition.
> - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the
> reference manual.
>
> Changes in v2:
> - Rebase against latest master.
>
> arch/arm/cpu/armv7/mx6/soc.c | 4 ++--
> arch/arm/include/asm/arch-mx25/imx-regs.h | 8 ++++++--
> arch/arm/include/asm/arch-mx27/imx-regs.h | 2 +-
> arch/arm/include/asm/arch-mx31/imx-regs.h | 9 +++++++--
> arch/arm/include/asm/arch-mx35/imx-regs.h | 7 ++++++-
> arch/arm/include/asm/arch-mx5/imx-regs.h | 6 +++++-
> arch/arm/include/asm/arch-mx6/imx-regs.h | 19 +++++++------------
> board/freescale/mx6qsabreauto/mx6qsabreauto.c | 5 ++++-
> 8 files changed, 38 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index 69b8487..fc436fb 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -172,8 +172,8 @@ void enable_caches(void)
> #if defined(CONFIG_FEC_MXC)
> void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
> {
> - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
> - struct fuse_bank *bank = &iim->bank[4];
> + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
> + struct fuse_bank *bank = &ocotp->bank[4];
> struct fuse_bank4_regs *fuse =
> (struct fuse_bank4_regs *)bank->fuse_regs;
>
> diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
> index 5f4b543..99c32d4 100644
> --- a/arch/arm/include/asm/arch-mx25/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
> @@ -113,8 +113,12 @@ struct iim_regs {
> u32 iim_sdat;
> u32 iim_prev;
> u32 iim_srev;
> - u32 iim_prog_p;
> - u32 res1[0x1f5];
> + u32 iim_prg_p;
> + u32 iim_scs0;
> + u32 iim_scs1;
> + u32 iim_scs2;
> + u32 iim_scs3;
> + u32 res1[0x1f1];
> struct fuse_bank {
> u32 fuse_regs[0x20];
> u32 fuse_rsvd[0xe0];
> diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
> index 2f6c823..aee058f 100644
> --- a/arch/arm/include/asm/arch-mx27/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
> @@ -176,7 +176,7 @@ struct iim_regs {
> u32 iim_sdat;
> u32 iim_prev;
> u32 iim_srev;
> - u32 iim_prog_p;
> + u32 iim_prg_p;
> u32 iim_scs0;
> u32 iim_scs1;
> u32 iim_scs2;
> diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
> index 3f58318..f67f49c 100644
> --- a/arch/arm/include/asm/arch-mx31/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
> @@ -68,7 +68,7 @@ struct cspi_regs {
> u32 test;
> };
>
> -/* IIM Control Registers */
> +/* IIM control registers */
> struct iim_regs {
> u32 iim_stat;
> u32 iim_statm;
> @@ -80,11 +80,16 @@ struct iim_regs {
> u32 iim_sdat;
> u32 iim_prev;
> u32 iim_srev;
> - u32 iim_prog_p;
> + u32 iim_prg_p;
> u32 iim_scs0;
> u32 iim_scs1;
> u32 iim_scs2;
> u32 iim_scs3;
> + u32 res[0x1f1];
> + struct fuse_bank {
> + u32 fuse_regs[0x20];
> + u32 fuse_rsvd[0xe0];
> + } bank[3];
> };
>
> struct iomuxc_regs {
> diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
> index 7f337be..64546d2 100644
> --- a/arch/arm/include/asm/arch-mx35/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
> @@ -262,11 +262,16 @@ struct iim_regs {
> u32 iim_sdat;
> u32 iim_prev;
> u32 iim_srev;
> - u32 iim_prog_p;
> + u32 iim_prg_p;
> u32 iim_scs0;
> u32 iim_scs1;
> u32 iim_scs2;
> u32 iim_scs3;
> + u32 res1[0x1f1];
> + struct fuse_bank {
> + u32 fuse_regs[0x20];
> + u32 fuse_rsvd[0xe0];
> + } bank[3];
> };
>
> /* General Purpose Timer (GPT) registers */
> diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
> index a71cc13..b237d5f 100644
> --- a/arch/arm/include/asm/arch-mx5/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
> @@ -499,7 +499,7 @@ struct iim_regs {
> u32 sdat;
> u32 prev;
> u32 srev;
> - u32 preg_p;
> + u32 prg_p;
> u32 scs0;
> u32 scs1;
> u32 scs2;
> @@ -508,7 +508,11 @@ struct iim_regs {
> struct fuse_bank {
> u32 fuse_regs[0x20];
> u32 fuse_rsvd[0xe0];
> +#if defined(CONFIG_MX51)
> } bank[4];
> +#elif defined(CONFIG_MX53)
> + } bank[5];
> +#endif
> };
>
> struct fuse_bank0_regs {
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index 0e4d8fa..680e752 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -229,7 +229,6 @@
>
> #define CHIP_REV_1_0 0x10
> #define IRAM_SIZE 0x00040000
> -#define IMX_IIM_BASE OCOTP_BASE_ADDR
> #define FEC_QUIRK_ENET_MAC
>
> #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
> @@ -258,12 +257,6 @@ struct src {
> u32 gpr10;
> };
>
> -/* OCOTP Registers */
> -struct ocotp_regs {
> - u32 reserved[0x198];
> - u32 gp1; /* 0x660 */
> -};
> -
> /* GPR3 bitfields */
> #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
> #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
> @@ -438,7 +431,7 @@ struct cspi_regs {
> ECSPI5_BASE_ADDR
> #endif
>
> -struct iim_regs {
> +struct ocotp_regs {
> u32 ctrl;
> u32 ctrl_set;
> u32 ctrl_clr;
> @@ -449,9 +442,9 @@ struct iim_regs {
> u32 rsvd1[3];
> u32 read_ctrl;
> u32 rsvd2[3];
> - u32 fuse_data;
> + u32 read_fuse_data;
> u32 rsvd3[3];
> - u32 sticky;
> + u32 sw_sticky;
> u32 rsvd4[3];
> u32 scs;
> u32 scs_set;
> @@ -466,7 +459,7 @@ struct iim_regs {
>
> struct fuse_bank {
> u32 fuse_regs[0x20];
> - } bank[15];
> + } bank[16];
> };
>
> struct fuse_bank4_regs {
> @@ -477,7 +470,9 @@ struct fuse_bank4_regs {
> u32 mac_addr_low;
> u32 rsvd2[3];
> u32 mac_addr_high;
> - u32 rsvd3[0x13];
> + u32 rsvd3[0xb];
> + u32 gp1;
> + u32 rsvd4[7];
> };
>
> struct aipstz_regs {
> diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> index aec3286..a3afa58 100644
> --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> @@ -179,7 +179,10 @@ static int mx6sabre_rev(void)
> * i.MX6Q ARD RevB: 0x02
> */
> struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
> - int reg = readl(&ocotp->gp1);
> + struct fuse_bank *bank = &ocotp->bank[4];
> + struct fuse_bank4_regs *fuse =
> + (struct fuse_bank4_regs *)bank->fuse_regs;
> + int reg = readl(&fuse->gp1);
> int ret;
>
> switch (reg >> 8 & 0x0F) {
>
--
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